CDC Solution Lunch & Learn, Sign Up Request

With verification of ASICs and FPGAs representing greater than 50% of the overall development cycle, why is it 69% of ASICs are behind schedule and 78% of FPGAs have non-trivial bugs that escape into production? A major contributor is metastability issues.

Metastability is caused by improper clocking architectures and typically escapes detection during simulation. It is produced by signals and busses crossing clock domain boundaries without proper synchronization. This Lunch and Learn will explore common clock domain crossing issues and synchronization strategies, including how to detect CDC issues as you code and how to validate systems with encrypted IP are CDC clean.

Sign up to learn how Blue Pearl’s Visual Verification Suite can solve Clock Domain Crossing issues.
Note: All Lunch & Learns will take place at the Blue Pearl booth #1120