“Blue Pearl Software’s latest capability allows us to selectively weigh logic elements and rapidly determine the longest paths rather than wait for long and expensive synthesis runs, thus enabling us to provide reliable products while reducing our design cycle.”
Carl Ruggiero, CEO, Trilinear Technologies
“Blue Pearl Software’s latest tool allows us to rapidly view design analysis results, including clock domain crossings and timing constraints, ensuring that our customers receive the highest quality verification IP available at this time.”
Samir Shroff, VP Engineering, Sibridge Technologies
“Blue Pearl has allowed us to create a low risk, predictable development cycle that helps generate accurate RTL code, reducing time-consuming iterations.”
Steve Presant, VP of Engineering, c2 Microsystems
“At Fujitsu, we use Analyze RTL™ from Blue Pearl Software to find bugs in the netlist early when they are easier to fix. From our experience, we can find bugs that could potentially save a tapeout.”
Mike James, Director, VLSI Technology, Fujitsu
“Create quickly generated timing exception constraints that improved the timing on our design by 30% after synthesis and placement in a Magma flow.”
Joe Dao, CAD Manager, Aeluros
“We use Create to generate timing exceptions for our challenging design blocks for Palmchip SoC Platform and IP blocks and have found that Cobalt runs very fast and produces accurate constraints at RTL.”
Jauher Zaidi, CEO Palmchip Corporation
