Blue Pearl Software is a company developing high-level language EDA products that improve the productivity of the ASIC/FPGA design flows. If you are ready to embark on an exciting long-term career opportunity and grow rapidly with us, please send your resume to firstname.lastname@example.org
Senior Software Development Engineer
Blue Pearl Software is looking for a talented, self-driven and motivated software engineer to be part of our RTL and Timing Constraint Analysis team in Santa Clara , CA The selected candidate will be involved in delivering robust best-in-class tools for RTL and timing constraint analysis to our customers. The position involves working with marketing and applications engineering to identify, architect and implement new features and resolve customer issues.
1. Ph.D./ M.S in EE with 7+ years of relevant experience
2. Strong foundation in Software Engineering practices
3. Experience with C++ object oriented programming and C, PERL and TCL
4. Excellent communication and problem solving skills
5. Knowledge of RTL analysis and clock domain crossing analysis
6. Must have developed complex new features in front-end EDA products
7. Experience in timing analysis, synthesis or formal verification and knowledge of TCL/TK and QT is a plus .
Software Development Engineer
We are looking for motivated, highly capable C/C++ software engineers to help develop advanced timing constraint generation, timing constraint verification, RTL analysis and functional verification tools. Work includes RTL synthesis of Verilog, VHDL and System Verilog; and developing timing constraint generation, verification and static RTL analysis tools.
Masters degree and 5+ years EDA experience or Bachelors and 7+ years of experience in EDA. Strong knowledge of and experience in C/C++ programming and scripting languages (Tcl,Perl) required. Previous experience in developing RTL synthesis, analysis or simulation tools required. Knowledge of and experience with Verilog,VHDL a requirement. You must understand high level model generation, netlist creation, traversal and analysis techniques. Knowledge of System Verilog, strong skills in Lex and Yacc, and knowledge of the .lib format are also desirable. Knowledge of PSL or SVA assertion languages is a plus.
Field Applications Engineers – Bay Area
We are looking for design engineers with real experience of how to get the best out of ASIC and/or FPGA synthesis tools. Your skill set will include an excellent understanding of real-world use of synthesis tools and flows, with emphasis on timing constraints (clocks and most importantly: timing exceptions) and clock domain crossing issues.
Knowledge of Verilog is required. Knowledge of VHDL and/or SystemVerilog would be an advantage.
You must be prepared to make the leap into Applications Engineering and have the necessary interpersonal skills to deal with customers and the technical skills to resolve and communicate technical issues for customers. We are a start-up company and flexibility will be required from you and will provide opportunities for development to you!
Knowledge of Verilog is required.
Knowledge of VHDL and/or SystemVerilog would be an advantage.
Some travel required.
All applications will be treated in confidence.
No recruiters, please: direct principals only. Please email your resume in pdf format.
Software QA Engineer – Bay Area
CS degree with knowledge of hardware design languages (Verilog/VHDL) or EE degree with strong CS background.
Develop testcases for white/black box testing of RTL analysis/CDC tool.
Analyse results of test runs and advise on remedial actions.
Attention to details is vital: analysis of test results needs to be accurate and fast.
Automation of test systems: running and analysis.
Actively search for opportunities for process improvements.
Flexible attitude: able to switch tasks and be responsive to the needs of peers and company priorities.
Work with applications engineers to provide advice on best practices and process bugs.
Manage bugs reports from submission to closure.
Fluency in scripting languages (bash and perl required).
Knowledge of hardware design languages (Verilog/VHDL) Understanding of hardware synthesis (Synopsys DC or Synplify) would be a plus.
Knowledge of Linux and Windows.
Senior Field Applications Engineer :Bay Area/West Coast
This position is responsible for the technical aspects of selling Blue Pearl Software products in the San Francisco Bay Area and Southern California. This is a new position due to growth in the company with future opportunities for a Field Applications Management career path. The Candidate must have a proven track record working in the EDA software sales environment. The Candidate must have strong technical acumen in all aspects of end-user FPGA design. This individual must be able to manage multiple sales campaigns, communicate the customer technical requirements internally and bring together the technical resources necessary to close sales.
Desired Skills & Experience
• Must be able to travel at least 25% of the time
• BS with a minimum of 7-8 years of relevant experience or MS with a minimum of 5 years of experience
• In-depth understanding of the FPGA end-user design process
• Thorough knowledge of Linux and Windows compute environments
• Thorough knowledge of RTL languages (Verilog, SystemVerilog, VHDL)
• Thorough knowledge of at least one scripting language such as Perl/TCL/Shell
• Demonstrated ability to work independently with customers to drive product evaluations to successful completion
• Demonstrated ability to communicate technical issues with company management to achieve sales success
• Thorough knowledge of ASIC and FPGA development tools and their associated flows
Preferred Additional Skills
• Actual FPGA design experience using VHDL
• Actual ASIC design experience using SystemVerilog
• Demonstrated technical writing expertise via published application notes, articles and technical papers.
E-mail your Resume: email@example.com, firstname.lastname@example.org