Employment Opportunities
Blue Pearl Software is a new company developing high-level language EDA products that improve the productivity of the ASIC/FPGA design flows. If you are ready to embark on an exciting long-term career opportunity and grow rapidly with us, please send your resume to
Current Openings
Senior Software Development Engineer
We are looking for talented engineers to join our R&D team. As part of the team, you will design, develop and debug EDA software used for timing constraint generation, verification and debugging. You will independently analyze and create solutions for complex software products and will be responsible for all phases of software development from initial problem identification and solution specification to final testing and debugging.
Requirements
M.S. or Ph.D. in EE/CS plus 10 years of industry related experience in timing analysis and synthesis. Must possess very strong expertise in C/C++, and strong experience with Verilog and VHDL languages. Must have very strong knowledge of timing constraint and timing exception generation in SDC format. Strong experience in and knowledge of EDA, and the digital design process also required. Practical knowledge and experience in the development of timing analysis and synthesis a must. Strong spoken and written communication skills a requirement. Knowledge of logic simulation and formal verification also desirable. Knowledge of FPGA synthesis and FPGA timing constraint formats a plus.
Software Development Engineer
We are looking for motivated, highly capable C/C++ software engineers to help develop advanced timing constraint generation, timing constraint verification, RTL analysis and functional verification tools. Work includes RTL synthesis of Verilog, VHDL and System Verilog; and developing timing constraint generation, verification and static RTL analysis tools.
Requirements
Masters degree and 5+ years EDA experience or Bachelors and 7+ years of experience in EDA. Strong knowledge of and experience in C/C++ programming and scripting languages (Tcl,Perl) required. Previous experience in developing RTL synthesis, analysis or simulation tools required. Knowledge of and experience with Verilog and VHDL a requirement. You must understand high level model generation, netlist creation, traversal and analysis techniques. Knowledge of System Verilog, strong skills in Lex and Yacc, and knowledge of the .lib format are also desirable. Knowledge of PSL or SVA assertion languages is a plus.
Senior Field Application Engineer
We are looking for motivated, highly capable Field Application Engineers to support advanced timing constraint generation, timing constraint verification, RTL analysis and functional verification tools. You will work with sales to qualify potential customers for Blue Pearl's timing constraint generation, verification and RTL analysis products, demonstrate products to qualified potential customers, engage in structured evaluations with potential customers - setting and working towards measurable milestones. You will also liaise with sales and engineering to help progression towards a product sale and work closely with R&D to provide feedback on tool issues and opportunities for new product features, and future directions of the Blue Pearl tool suite.
Requirements
7+ years FAE experience supporting and benchmarking timing analysis and synthesis solutions. Experience in selling and benchmarking timing analysis, formal verification and synthesis tools. MS in Electrical/Computer Engineering. Very strong customer interaction, communication and presentation skills. Must be highly self-motivated and driven to succeed. Requires PrimeTime timing analysis and DC experience, and strong Verilog/VHDL expertise and logic design skills. PC/PKS and FPGA synthesis experience a plus.
Field Application Engineer
We are looking for motivated, highly capable Field Application Engineers to support advanced timing constraint generation, timing constraint verification, RTL analysis and functional verification tools. You will work with sales to qualify potential customers for Blue Pearl's timing constraint generation, verification and RTL analysis products, demonstrate products to qualified potential customers, engage in structured evaluations with potential customers - setting and working towards measurable milestones. You will also liaise with sales and engineering to help progression towards a product sale and work closely with R&D to provide feedback on tool issues and opportunities for new product features, and future directions of the Blue Pearl tool suite.
Requirements
3-5 years FAE experience supporting and benchmarking timing analysis and synthesis solutions. Experience in selling and benchmarking timing analysis, formal verification and synthesis tools. BS-MS in Electrical/Computer Engineering. Very strong customer interaction, communication and presentation skills. Must be highly self-motivated and driven to succeed. Requires PrimeTime timing analysis and DC experience, and strong Verilog/VHDL expertise and logic design skills. PC/PKS and FPGA synthesis experience a plus.
