Blue Pearl Software Inc. http://www.bluepearlsoftware.com FPGA Designers, ASIC Designers, clock domain, Clock Domain Crossing (CDC), False Path, Multi-Cycle Path, SDC constraints, SDC, linting, DRC, timing constraints, design rules, design compliance, RTL analysis, timing closure, assertion, SVA, PSL. Fri, 17 May 2013 20:47:47 +0000 en hourly 1 Brian Daellenbach, President of Northwest Logic http://www.bluepearlsoftware.com/brian-daellenbach-president-of-northwest-logic/ http://www.bluepearlsoftware.com/brian-daellenbach-president-of-northwest-logic/#comments Thu, 28 Jun 2012 21:45:40 +0000 Shakeel http://www.bluepearlsoftware.com/?p=2583 “Using Analyze, we have identified and resolved coding issues that help us maximize the quality of our IP Cores”

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]]> “Using Analyze, we have identified and resolved coding issues that help us maximize the quality of our IP Cores”

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]]> http://www.bluepearlsoftware.com/brian-daellenbach-president-of-northwest-logic/feed/ 0 Blue Pearl at DAC 2012 http://www.bluepearlsoftware.com/blue-pearl-at-dac-2012/ http://www.bluepearlsoftware.com/blue-pearl-at-dac-2012/#comments Fri, 11 May 2012 01:10:26 +0000 Shakeel http://www.bluepearlsoftware.com/?p=2491 Booth #714

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]]> Booth #714

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]]> http://www.bluepearlsoftware.com/blue-pearl-at-dac-2012/feed/ 0 Carl Ruggiero, CEO, Trilinear Technologies. http://www.bluepearlsoftware.com/carl-ruggiero-ceo-trilinear-technologies/ http://www.bluepearlsoftware.com/carl-ruggiero-ceo-trilinear-technologies/#comments Thu, 27 Oct 2011 20:08:27 +0000 Shakeel http://www.bluepearlsoftware.com/?p=2130 “Blue Pearl Software’s latest capability allows us to selectively weigh logic elements and rapidly determine the longest paths rather than wait for long and expensive synthesis runs, thus enabling us to provide reliable products while reducing our design cycle.”

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]]> “Blue Pearl Software’s latest capability allows us to selectively weigh logic elements and rapidly determine the longest paths rather than wait for long and expensive synthesis runs, thus enabling us to provide reliable products while reducing our design cycle.”

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]]> http://www.bluepearlsoftware.com/carl-ruggiero-ceo-trilinear-technologies/feed/ 0 Samir Shroff, VP Engineering, Sibridge Technologies. http://www.bluepearlsoftware.com/samir-shroff-vp-engineering-sibridge-technologies/ http://www.bluepearlsoftware.com/samir-shroff-vp-engineering-sibridge-technologies/#comments Thu, 27 Oct 2011 20:07:06 +0000 Shakeel http://www.bluepearlsoftware.com/?p=2122 “Blue Pearl Software’s latest tool allows us to rapidly view design analysis results, including clock domain crossings and timing constraints, ensuring that our customers receive the highest quality verification IP available at this time.”

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]]> “Blue Pearl Software’s latest tool allows us to rapidly view design analysis results, including clock domain crossings and timing constraints, ensuring that our customers receive the highest quality verification IP available at this time.”

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]]> http://www.bluepearlsoftware.com/samir-shroff-vp-engineering-sibridge-technologies/feed/ 0 Steve Presant, VP of Engineering, C2 Microsystems http://www.bluepearlsoftware.com/excepteur-sint-occaecat-cupidatat-2/ http://www.bluepearlsoftware.com/excepteur-sint-occaecat-cupidatat-2/#comments Fri, 04 Feb 2011 18:38:09 +0000 Shakeel http://localhost/ebiz/?p=1148 “Blue Pearl has allowed us to create a low risk, predictable development cycle that helps generate accurate RTL code, reducing time-consuming iterations.”

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]]> “Blue Pearl has allowed us to create a low risk, predictable development cycle that helps generate accurate RTL code, reducing time-consuming iterations.”

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]]> http://www.bluepearlsoftware.com/excepteur-sint-occaecat-cupidatat-2/feed/ 0 Joe Dao, CAD Manager, Aeluros http://www.bluepearlsoftware.com/mrs-randa/ http://www.bluepearlsoftware.com/mrs-randa/#comments Tue, 29 Jun 2010 13:32:36 +0000 Shakeel http://imediautama.com/demo/vulcan/?p=209 “Create quickly generated timing exception constraints that improved the timing on our design by 30% after synthesis and placement in a Magma flow.”

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]]> “Create quickly generated timing exception constraints that improved the timing on our design by 30% after synthesis and placement in a Magma flow.”

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]]> http://www.bluepearlsoftware.com/mrs-randa/feed/ 0 Jauher Zaidi, CEO Palmchip Corporation http://www.bluepearlsoftware.com/jauher-zaidi-ceo-palmchip-corporation/ http://www.bluepearlsoftware.com/jauher-zaidi-ceo-palmchip-corporation/#comments Tue, 29 Jun 2010 03:57:12 +0000 Shakeel http://imediautama.com/demo/vulcan/?p=29 “We use Create to generate timing exceptions for our challenging design blocks for Palmchip SoC Platform and IP blocks and have found that Create runs very fast and produces accurate constraints at RTL.”

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]]> “We use Create to generate timing exceptions for our challenging design blocks for Palmchip SoC Platform and IP blocks and have found that Create runs very fast and produces accurate constraints at RTL.”

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]]> http://www.bluepearlsoftware.com/jauher-zaidi-ceo-palmchip-corporation/feed/ 0 Mike James, Director, VLSI Technology, Fujitsu http://www.bluepearlsoftware.com/mike-james-director-vlsi-technology-fujitsu/ http://www.bluepearlsoftware.com/mike-james-director-vlsi-technology-fujitsu/#comments Thu, 24 Jun 2010 13:56:22 +0000 Shakeel http://localhost/vulcan-demo/?p=359 “At Fujitsu, we use Analyze RTL Analysis from Blue Pearl Software to find bugs in the netlist early when they are easier to fix. From our experience, we can find bugs that could potentially save a tapeout.”

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]]> “At Fujitsu, we use Analyze RTL Analysis from Blue Pearl Software to find bugs in the netlist early when they are easier to fix. From our experience, we can find bugs that could potentially save a tapeout.”

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