Visual Verification Suite Release Notes
Contents:
Visual Verification Suite -- Release 2018.1 (Build
2018.1.47973)
August 15, 2018
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List of Key Features
- Updates to License Server Daemons & Edit/Replace License File
Needed
- Updated to FlexLM version 11.16
- If you are using a floating license, you must update to the
latest bluepsd and lmgrd daemons
- These can be found in the
<installation>/FLEXnet/<platform> directory
- Use of the "bluepsd" license daemon under Windows will require
installation of the appropriate Visual C++ Redistributable Packages for
Visual Studio 2013
- This update also necessitates a new license file, or editing
existing license files as follows:
- On the FEATURE gui line, delete the string just before
the final backslash (shown in bold in the following example)
- FEATURE gui bluepsd 2019.01 31-jan-2019 1
69A3B800F92A \
- License file editing may require system administrator
privileges
- Starter Edition
- Free, restricted-use license
- 45 day limit
- SDC and Custom UGC not available
- Requires internet connection
- Designs larger than 1000 SLOC will not load
- Make license request via Licensing Wizard (in the tool, or now
available as a separate download)
- Editor enhancements
- HDL Viewer/Editor has programming enhancements
- Highlighting and moving between matching brackets
- Text Report Enhancements
- Expanded Source Lines of Code (SLOC) report
- New Cyclic Registers report
- GUI Updates
- New system for finding missing files during design load
- New option for allowing real (non-integer) values as variables in
Verilog
- Enhancements to VHDL File Design Unit Location Detection
- Check ENTITY_ARCH_FILELOC now has an option to flag any single
entity/architecture pair not residing in their own file
(force_entity_single_arch_file)
- Check CONFIG_FILELOC now has an option to flag any configuration
not residing in its own file
(isolate_configuration_fileloc)
- Obsolete and deprecated items
- Check NS_NAME and message BPS-0266
- Replaced by STATE_VAR_NAME and BPS-0946/7
- New Checks
- MCI_WITH_DEFAULT - Case items are missing for case statement with
default
- NAME_ANALYSIS_KEYWORD - Report on naming for language
keywords
- NAME_ANALYSIS_PORT_DATA_TYPES - Report on naming of port data
types
- NAME_ANALYSIS_LIBRARIES - Report on naming for libraries
- UNLABELED_LOOP_STATEMENTS - Report on labeling of loops
- LATCH_CREATED - Flag all latches, inferred or otherwise
- STATE_VAR_NAME - Report on naming of FSM states
- FSM_NO_HCCS - Report on FSMs using hard-coded constants
- FSM_USE_TWO_STATE_VAR - Report on single-process FSMs not using
two-state register variables
- UNCONSTRAINED_INT - Report on integers with no range
specification (VHDL only)
- EXPLICIT_INSTANTIATION_PARAM_NAMING - Report on instantiations
that do not use explicit names for the parameters/generics.
- NAME_ANALYSIS_DATA_TYPES - Report on naming of data
types
- NO_VARIABLE_DECLS - Report variable declarations
- NO_ALIAS_DECLS - Report alias declarations
- NO_FILE_DECLS - Report file declarations
- NO_FILE_DECLS - Report file declarations
- NAME_ANALYSIS_OPERATOR_NAMES - Report on operator names
- NAME_ANALYSIS_OPERATOR_PARAMETER_NAMES - Report on operator
parameter names
- NAME_ANALYSIS_OPERATOR_PARAMETER_TYPE_NAMES - Report on operator
parameter type names
- NAME_ANALYSIS_OTHERS_ASSIGNMENTS - Report on VHDL
Others-assignment names
- New Messages
- BPS-0931 - Case items are missing for case statement with
default
- BPS-0932/3 - Apply naming criteria to language keywords, allowed
and disallowed
- BPS-0934/5 - Apply naming criteria to port data types, allowed
and disallowed
- BPS-0936/7 - Apply naming criteria to libraries, allowed and
disallowed
- BPS-0938 - Flag processes that do not have a closing
label
- BPS-0939 - Flag blocks that do not have a closing label
- BPS-0940 - Flag loops that do not have next or exit
labels
- BPS-0941 - Flag loops that do not have a label or a closing
label
- BPS-0942/3 - Apply naming criteria to HDL file names
- BPS-0944 - SLOC exceeded for Starter Edition
- BPS-0945 - Phone Home has timed out
- BPS-0946/7 - Apply naming criteria to FSM state names, allowed
and disallowed
- BPS-0948 - Report on any latches in the design
- BPS-0949 - Flag deprecated messages
- BPS-0950 - Flag FSMs using hard-coded constants
- BPS-0951 - Flag single-process FSMs not using two-state register
variables
- BPS-0952 - Flag integers with no range specification (VHDL
only)
- BPS-0953 - Flag instantiations that do not use explicit names for
the parameters/generics.
- BPS-0954/5 - Apply naming criteria to data types, allowed and
disallowed
- BPS-0956 - Flag variable declarations
- BPS-0957 - Flag alias declarations
- BPS-0958 - Flag file declarations
- BPS-0959/960 - Apply naming criteria to operator names, allowed
and disallowed
- BPS-0961/2 - Apply naming criteria to operator parameter names,
allowed and disallowed
- BPS-0963/4 - Apply naming criteria to operator parameter type
names, allowed and disallowed
- BPS-0965/6 - Apply naming criteria to VHDL Others-assignment
names, allowed and disallowed
- Known Issues
- Changed command line default value for the configuration
variable clock_detection_enabled_via_dffs
- Now defaults to true, matching the default value in the
GUI
- Similar default value changes for variables
sdc_write_split_buses, sdc_write_gen_get_nets,
sdc_write_comment_out_hierarchy_separator, and
sdc_write_expand_vector_q
- Platforms Supported
- Windows 7, 8.1 and 10, 64 bit
- CentOS/Red Hat Enterprise Linux 6.x
User Enhancements
- #2654 - Improved support for bidirects in User Grey Cell
Editor
- #2692 - Automatically select Vivado technology when enabling
Xilinx from Design Settings
- #2693 - Users can now delete source file from the file list with
the RMB
- #2695 - Files listed in the transcipt can now be located in the
file list using the RMB
- #2696 - Updated functionality for adding files
recursively
- #2720 - Added support for Intel QSF loading Verilog
macros/`defines
- #2743 - Support for Axcelerator library from Microsemi in
SynplifyPRO project files
- #2744 - Fix for VHDL 2008 support in Synplify Project
files
- #2723 - Updated Altera scfifo and dcfifo cells
- #2762 - Support for nested file lists relative to nested file
location
- #2765 - Support for Vivado-style .mif file location
calls
- #2763 - Scalar rips of buses are now allowed in UGC
equations
- #2781/2 - Altera library updates for FIFO components
- #2683 - Handle UGC with output having asynch reset without any
data equation
- #2792 - Improved feedback for improper regular expressions in CDC
Waivers
List of Bugs Fixed
- #1235 - Fixed issue for false paths ending in liberty
module
- #2152 - Fixed issue with spurrious VERI-9001 message
- #2335 - Fixed CDC Viewer issue with bused clocks
- #2401 - Fixed bitsize reporting issue
- #2450 - Fixed issue with external CDC constraints
- #2473 - Fixed issue with FILE_HEADER
check
- #2490 - Fix for reporting of clocks extracted from
buses
- #2503 - Recognize VHDL FSMs with synchronous resets
- #2546 - Fixed error for constant function call
- #2558 - Recognize VHDL FSMs that use rising_edge
construct
- #2612 - Recognizing more FSMs
- #2691 - Splash screen no longer blocks popups
- #2694 - Deleting the file path while re-naming from the file list
is no longer allowed
- #2702 - Design load speedup
- #2704 - Improved support for customizing default settings using
bps_setup.tcl file
- #2705 - Red/Blue arrows are now compatible with ExtraInfo
messages
- #2709 - Improved recognition of VHDL FSMs
- #2711 - No longer report constant nets as undriven
- #2714 - No longer report clocks as unregistered
- #2719 - Fixed STARC documentation issue
- #2581 - Recognizing even more FSMs
- #2740 - Fixed bad flagging of WOR net as
multi-driver
- #2752 - Fixed bad flagging of missing port
- #2745 - Fixed library mapping for Microsemi from
Synplify
- #2757 - Fixed invalid Duplicate Case Item message
- #2766 - Fix for FSM analysis with two case statements on the same
ID
- #2767 - Fix for UNUSED_FUNC_INPUT on vhdl
- #2772 - Documentation for NAME_ANALYSIS_FILENAMES enhanced and
clarified
- #2764 - Parameters using nested structures are now correctly
expanded for instantiated modules
- #2780 - Localparam inside generate now properly seen as
constant
- #2783 - Fix for postponed vhdl processes
- #2784 - Fix for configurations not working in RTL elab AFTER
static elab
- #2789 - Fix for clock names in VHDL SDC files
- #2794 - Fix for real value being assigned
- #2795 - Improved evaluation of config parameters
- #2797 - Fix for translate_on/off attributes for VHDL
- #2796 - Updated to FlexLM version 11.16
- #2800 - Updated to FlexLM version 11.16
Visual Verification Suite -- Release 2017.3
(2017.3.43549)
November 4, 2017
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List of
Key Features
- Performance improvements for CDC
- Management Dashboard now has a table view
- In addition to viewing the data as a graph, you can now view the
data in table form
- GUI Updates
- Improved User Grey Cell Editor
- Allows simultaneous editing of multiple signals
- Other usability enhancements
- Design Settings and Analysis Settings dialog box menu items are
now searchable
- Expanded ability to save table output data directly to CSV files
is now found in:
- Analysis Report
- Text Report
- Management Dashboard
- Formal Verification Viewer
- Results Comparison
- Results Comparison Summary
- New Design Settings page to allow excluding files loaded via
External Projects
- Design Settings → Languages page now includes Gate Level
Verilog and Verilog Header extensions
- Design Settings → Clocks page now includes Disable ACE
check-box
- Design Settings → General page now includes Shorten Long
Module Names check-box
- Advanced stack reporting on internal errors
- Simplifies the interface for customer issues
- Obsolete and deprecated items
- The check BUS_CLOCK_FOUND is repaced by BUS_OBJECT_FOUND
- New Messages
- BPS-0927 - Overridden Assignment is not performed for very wide
signals
- BPS-0928 - Zero or negative values for repeat statements are
flagged
- BPS-0929 - File matching ignore file naming criterion is
ignored
- BPS-0930 - File matching ignore file extension criterion is
ignored
- Known Issues
- Platforms Supported
- Windows 7, 8.1 and 10, 64 bit
- CentOS/Red Hat Enterprise Linux 6.x
User
Enhancements
- #2638 - Xilinx XPR reader now supports $PSRCDIR variable in File
element
- #2640 - Xilinx XPR reader now supports use of non-default
VHDL libraries
- #2659 - Documentation enhancements for UNCONNECTED checks
and more
- #2661 - Better support for tracing of intentionally
unconnected signals
List of Bugs Fixed
- #2644 - Fixed issue with INVALID_COMPARISON check
- #2649 - Fixed improper reporting of state transition
- #2645 - Fixed invalid Missing IF block assignment
message
- #2647 - Fixed issue with DUPLICATE_TERM check
- #2648 - Fixed issue with UNNAMED_BLOCKS check option
report_all_unnamed_gen_stmts
- #2649 - Fixed invalid state transition reported for FSM
- #2650 - Fixed issue with OVERRIDDED_ASSIGN check
- #2662 - Fixed check INVALID_COMPARISON not reporting on always
true equation
- #2663 - DUPLICATE_TERM check now correctly handles constant used
for comparison
- #2664 - Fixed DUPLICATE_TERM check wrongly warning about a null
string '' as duplicate
- #2672 - Fixed issue regarding VHDL parsing of unsigned
signal
- #2686 - No longer suppressing clocks generated from Xilinx
PLL
- #2687 - Fixed internal error on floating point
exception
- #2699 - Added VHDL capability to NO_INITIAL check
- #2700 - Improved VHDL analysis for MULTI_PORT check
- #2701 - Added new check MCI_WITH_DEFAULT
Visual Verification Suite -- Release 2017.2
(2017.2.42229)
July 25, 2017
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List of
Key Features
- Visual Verification Suite now accepts FPGA Vendor project
files
- Intel®/Altera Quartus® Prime
Software
- Microsemi® Libero® Design
Software
- Synopsys® Synplify® Pro
- Xilinx® Vivado® Design Suite
- Seamlessly load your design from Xilinx Vivado into Blue Pearl
VVS
- Automatically set ASIC and FPGA default options by vendor to
ensure Blue Pearl recommended checks are performed
- Visual Verification Suite's Management Dashboard can now track
FPGA vendor tool reports
- These reports are in addition to Blue Pearl Analyze, CDC, Waiver
and Design sign off reports
- This new capability is ideal for tracking in revision control
systems, design audits and reviews
- Import timing, power, and utilization data from FPGA vendor
tools:
- Intel/Altera Quartus Prime Software
- Microsemi Libero Design Software
- Xilinx Vivado Design Suite
- Create your own custom Management Dashboard reports
- Extended Support for Microsemi Libraries
- RTG4
- SmartFusion 2
- IGLOO 2
- Licensing support for the FLEXid-9 USB Dongle is now
added
- New Option
- Muxed clocks can now be seen as complex gated clocks
- Expanded and enhanced Basic Checks package
- The Basic Checks package includes all checks that are on
by default
- Expanded from 30 to 48 checks, based on customer
recommendations
- Replaced older DANG check for dangling nets with four more
specific UNCONNECTED checks
- Added fifteen other existing checks concerning resets, finite
state machines, and unsynthesizable constructs
- Interactive CLI runs are now distinct from Load runs
- Starting a command line run and executing commands other than
BPS::run
- E.g. Database queries, creating custom tables, etc.
- New GUI Behavior
- Users can now directly open a Tcl file when starting the GUI
- BluePearlVVE project.tcl
- This is an alternative to specifying a '.bps' file
- GUI Updates
- Design Settings → Clocks page now has automatic clock detection
options
- Clock Buses are now on a separate page under Design
Settings
- RMB feature in Design Browser allows creation of SDC command
placed into the clipboard
- CDC Viewer now has six additional categorizations of wide
double-register synch CDCs
- New Checks
- MISMATCH_CONSTANT_ASSIGN - Mismatched bit width involving
constants
- NAME_ANALYSIS_LABELS - Naming check for many kinds of Verilog and
VHDL labels
- DUPLICATE_TERM - Flag duplicate terms in expressions
- INVALID_COMPARISON - Flag conditionals that will be always true
or always false due to sign or size
- OVERRIDDEN_ASSIGN - Assignment overridded by new
assignment
- AMBIG_IFIFELSE - Flag ambiguous else clause in a nested if
statement
- New Messages
- BPS-0918 - Allowed label names
- BPS-0919 - Disallowed label names
- BPS-0920 - Mismatched Constant Assignment
- BPS-0921 - Error reading External Project
- BPS-0922 - External Project read successfully
- BPS-0923 - Duplicate Terms in Expression
- BPS-0924 - Invalid Comparison
- BPS-0925 - Check for multiple Assignments to the same
wire
- BPS-0926 - Flag ambiguous else clause in a nested if
statement
- Obsolete and deprecated items
- Check AUTO_DETECT_CLOCKS is replaced by configuration variable
clock_detection_enabled_via_dffs
- Check AUTO_DETECT_CLOCKS_LATCHES is replaced by configuration
variable clock_detection_enabled_via_latches
- Check PROC_LABEL is now part of the NAME_ANALYSIS_LABELS
check
- The configuration variable cdc_on_static_control_registers
has been replaced by suppress_cdc_from_scr
- Known Issues
- Platforms Supported
- Windows 7, 8.1 and 10, 64 bit
- CentOS/Red Hat Enterprise Linux 6.x
User
Enhancements
- #2462 - Add new check for ambiguous else clause in a nested if
statement (AMBIG_IFIFELSE)
- #2463 - Added new check for analyzing redundant sub-expressions
(DUPLICATE_TERM)
- #2465 - Flag conditionals that will be always true or always
false due to sign or size (INVALID_COMPARISON)
- #2528 - New check warns when a sized constant is assigned to a
constant of a different width variable
(MISMATCH_CONSTANT_ASSIGN)
- #2529 - Added option to flag unlabeled generate statements when
they are not within a block (set report_all_unnamed_gen_stmts true, check
UNNAMED_BLOCKS)
- #2530 - Check for multiple Assignments to the same wire
(DUPLICATE_TERM)
- #2590 - Added support for Microsemi IGLOO 2
- #2591 - Added support for Microsemi SmartFusion 2
- #2616 - Added option to allow muxed clocks to be seen as complex
gated clocks
- #2620 - Enhanced SDC Debug capability in GUI
- #2621 - Design Settings → Clocks page improved, separate Clock
Buses page
List of Bugs Fixed
- #2613 - Improved bit-width calculation
- #2619 - Allow loading of design despite SDC input file
errors
- #2623 - Fixed issue with set_case_analysis using hierarchical
pins
- #2624 - Fixed issue with indexing and localparams
- #2625 - Custom UGC License is no longer required to use UGC
files
- #2630 - Fix for SDC get_pins command used with VHDL
architectures
Visual Verification Suite -- Release 2017.1
(2017.1.40799)
March 18, 2017
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List of
Key Features
- Extended SDC and Tcl support
- Support for most common SDC commands
- Can be used to expand custom reporting capabilities
- Custom Checks
- Create a check to call a custom Tcl procedure that writes your
message to the database
- Formal Verification-based Features
- Identify multi-bit CDCs with guaranteed single-bit transitions
- Viewer tool for FV-based output
- Enhanced FSM Analysis
- More types of FSMs detected
- Additional non-static states and transitions detected
- Enhanced bit-wise evaluation of ITE statements
- GUI Changes
- Clock-to-clock false paths are now found on their own page
under CDC in the Analysis Settings dialog
- New page under Design Settings dialog for control
of Module options
- New Checks
- FSM_BOUNDS - Enables analysis of FSM case items up to the state
variable size
- ETB - Flags Empty THEN blocks
- UNUSED_FUNC_INPUT - Flags unused inputs of function
- PACK_BODY_LOC - Package Body and package declaration in the same
file
- CONFIG_FILELOC - Multiple configurations should not be defined in
the same file
- CONFIG_FILENAME - Configuration filenames should have correct
information
- MULT_ARCH - Multiple architectures for the same entity
- PROC_LABEL - Enable checking of VHDL process labels
- ENTITY_ARCH_FILELOC - Put VHDL architectures and entities in
separate files
- New Messages
- BPS-0889 - Ignored Tcl command
- BPS-0890 - Tcl search returned no objects
- BPS-0891 - Case out of bounds in FSM
- BPS-0892 - Import project unuspported
- BPS-0893 - Import project definition file error
- BPS-0894 - Import project execution error
- BPS-0895 - Missing IF assignment with previous assignment, no
latch created
- BPS-0896 - FSM State Found, informational message
- BPS-0897 - Empty Then Statement
- BPS-0898 - Unused Input to a Function
- BPS-0899 - Conditional Expression evaluates to a constant
1/0
- BPS-0900 - Conditional Expression evaluates to a constant
x/z
- BPS-0901 - Tcl command finds no clocks
- BPS-0902 - Multiple architectures and entities in file
- BPS-0903 - Package body location
- BPS-0904 - Configuration file location
- BPS-0905 - Configuration file name
- BPS-0906 - Process label naming
- BPS-0907 - False Path between Clocks
- BPS-0908 - Source clock neither port nor pin
- BPS-0909 - Named clock matches non-clock
- BPS-0910 - Redundant Path Found
- BPS-0911 - Redundant Path Overridden
- BPS-0912 - Multiple Architectures for Entity
- BPS-0913 - Custom Check Running
- BPS-0914 - Custom Check Finished with Error
- BPS-0915 - Custom Check Finished Successfully
- Obsolete and deprecated items
- Known Issues
- Specification of relative file locations for Tcl commands are now
always relative to the location where they are specified, not
necessarily to the home directory
- e.g. For a Tcl file in a subdirectory, files must be specified
relative to that subdirectory
- Platforms Supported
- Windows 7, 8.1 and 10, 64 bit
- CentOS/Red Hat Enterprise Linux 6.x
List of Bugs
Fixed
- #2460 - Improved utility of BluePearl pragmas for message
suppression
- #2515 - Added check and message for function input not being
used
- #2559 - Enhanced bit-wise evaluation of ITE
statements
- #2575 - Now recognizes interconnected state machines
- #2577 - Tcl help now provides return type
- #2579 - Fix for clock analysis issue
- #2580 - Multi-field parameters for file headers now allow
spaces
- #2583 - Fix for improperly inferred RAMs
- #2584 - Combinational Levels option works properly from the
GUI
- #2585 - Check MAX_LINES_PER_MODULE now works for VHDL
Architectures
- #2590 - Added support for Microsemi IGLOO 2
- #2591 - Added support for Microsemi SmartFusion 2
- #2594 - Fixed IBUFGDS in Xilinx library
Visual Verification Suite -- Release 2016.3
(2016.3.38678)
October 17, 2016
Return to Top
List of
Key Features
- New naming rule methodology
- Naming rules are now controlled by regular expressions
- More powerful and flexible control of naming rules
- New categories of objects, such as ports and constants, are added
to name checking
- New checks, new messages
- Updated VVE parsing engine
- Improved handling of reset detection, especially for
latches
- Updated algorithm for constant propagation
- Improved handling of three-state logic
- More closely duplicates the function of Verilog's bufif1
functional primitive
- New methodology for custom bps_setup.tcl files
- The old method of copying an entire private version of the
bps_setup.tcl file from the installation directory will no longer
work
- All bps_setup.tcl files are read sequentially
- Place only new portions of bps_setup.tcl file into
previous location
- For example, only commands for user-defined package
- User-defined locations for personalized bps_setup.tcl
file are now permitted
- New tcl commands available to remove packages
- See Reference Manual for more details
- GUI Changes
- Design Settings → Naming page has changed completely
- On the Design Settings → Clocks page, the
Automatic Detection checkboxes are gone
- They have been replaced by the AUTO_DETECT_CLOCKS checks
- The Preferences dialog now inculdes Startup Search
Path
- The built-in editor now supports indentation with tabs or
spaces
- The Design Settings → RAM Inferencing Analysis page
has been removed
- The options for the FANOUT check have moved from
Analysis Settings to Design Settings
- CLI Changes
- Dependent checks no longer automatically enable parent
checks
- E.g. enabling MULTIPLE_SYNCHRONIZATION by itself produces
BPS-0887 warning rather than automatically enabling
SYNCH_DATA_CONVERGES
- In GUI, enabling MULTIPLE_SYNCHRONIZATION still enables
SYNCH_DATA_CONVERGES
- The following messages are now applied individually rather than
collectively:
- BPS-0108 Unused Parameter
- BPS-0453 No Synchonous De-assertion of Reset
- BSP-0467 Parameter Reported
- Known Issues
- Platforms Supported
- Windows 7, 8.1 and 10, 64 bit
- CentOS/Red Hat Enterprise Linux 6.x
- New Checks
- NAME_ANALYSIS_GLOBAL - Global naming criteria
- NAME_ANALYSIS_MODULES - Module naming criteria
- NAME_ANALYSIS_PORTS - Port naming criteria
- NAME_ANALYSIS_SIGNAL - Signal naming criteria
- NAME_ANALYSIS_REGISTERS - Register naming criteria
- NAME_ANALYSIS_CLOCKS - Clock naming criteria
- NAME_ANALYSIS_RESETS - Reset naming criteria
- NAME_ANALYSIS_SETS - Set naming criteria
- NAME_ANALYSIS_CLOCKENABLE - Clock enable naming criteria
- NAME_ANALYSIS_INSTANCES - Instance naming criteria
- NAME_ANALYSIS_FUNCTION_NAME - Function naming criteria
- NAME_ANALYSIS_CONSTANTS - Constant, parameter, global, `define,
etc. naming criteria
- AUTO_DETECT_CLOCKS - Enable auto clock detection
- AUTO_DETECT_CLOCKS_LATCHES - Enable auto clock detection via
latches
- IDENTIFY_STATIC_CONTROL_REGISTERS - Name-based identification of
static control registers
- IDENTIFY_CLOCK_GATING_SIGNALS - Name-based identification of
clock gating signals
- IDENTIFY_RESET_SIGNALS - Name-based identification of reset
signals
- IDENTIFY_SET_SIGNALS - Name-based identification of set
signals
- IDENTIFY_DANGLING_SIGNALS - Name-based identification of dangling
signals
- IDENTIFY_DANGLING_PINS - Name-based identification of dangling
pins
- IDENTIFY_TIE_NETS - Name-based identification of nets tied to one
or zero
- New Messages
- BPS-0845 - Clock bus has been expanded
- BPS-0846 - Deprecated Tcl command or variable
- BPS-0847 - Deprecated Check
- BPS-0848 - Static Control Register found
- BPS-0849 - Check not enabled for message
- BPS-0850 - Invalid Naming Option
- BPS-0851 - BPS-0864 - Various naming criteria
- BPS-0865 - BPS-0878 - Various disallowed naming criteria
- BPS-0879 - BPS-0886 - Identified clocks and set/resets based on
names
- BPS-0887 - Parent check not enabled
- BPS-0888 - Module was black boxed at user request due to
missing/error
- Obsolete and deprecated items
- Check ALN (instead use regular expression .*_n for Active
Low)
- Check ALPHANUMERIC_NAMES ([a-zA-Z0-9_]* for Global)
- Check CCKN (instead use regular expression {${PARENT_CLOCK}}.*
for Internal Clocks)
- Check CKN (instead use regular expression clk.* for Clocks)
- Check DIS_NAME (instead use desired regular expression for
Global)
- Check MOD_INST_NAME (instead use regular expression {${MODULE}}.*
for Modules)
- Check NO_DOUBLE_UNDERSCORES (instead use disallowed regular
expression .*__.* for global)
- Check NO_START_UNDERSCORE (instead use disallowed regular
expression _.* for Global)
- Check REG_SUFFIX (instead use regular expression .*_reg for
Registers)
- Check RSTNAME (instead use regular expression .*rst for
Resets)
- Check START_ALPHA (instead use regular expression [a-zA-Z].* for
Global)
- Check UCCN (instead use regular expression [A-Z0-9_]* for
Constants)
- Message BPS-0035
- Message BPS-0036
- Message BPS-0037
- Message BPS-0038
- Message BPS-0236
- Message BPS-0258
- Message BPS-0259
- Message BPS-0260
- Message BPS-0261
- Message BPS-0262
- Message BPS-0263
- Message BPS-0568
- Message BPS-0569
- Message BPS-0570
- Message BPS-0571
- Message BPS-0572
- Message BPS-0573
- Message BPS-0574
- Message BPS-0575
- Message BPS-0576
- Message BPS-0606
- Message BPS-0607
List of Bugs
Fixed
- #2495 - Fixed lack of support for forceload/no BPSVDB in
GUI
- #2538 - Fix for reporting incorrect CDC destination
clock
- #2539 - Fix for clock bus port/net name issue
- #2540 - Analysis Report now able to sort on Check
Name
- #2542 - Now handles VHDL based bused clock
constraints
- #2553 - Fix for problem during dynamic checks
- #2554 - Environmental variable BPS_STARTUP_SEARCH_PATH augments
methodology for use of custom Tcl startup scripts
- #2556 - Parameters, used and unused, are now given messages
individually
- #2558 - Fixed output Clock from MMCME2 Xilinx Clock
Cell
- #2560 - Better commenting of decl handling
- #2561 - Fixed Design Browser double-click problem
- #2562 - Fixed Management Dashboard icon
- #2564 - Fixed VHDL comments in editor
- #2566 - Improved tab behavior in editor
- #2574 - The tcl 'puts' command now works with printf
characters
Blue Pearl Software Suite -- Release 2016.2
(2016.2.37438)
June 30, 2016
Return to Top
List of
Key Features
- Management Dashboard
- Histograms to summarize and track messages, CDCs, signoff
checklists, and waivers
- Design Signoff Checklists
- Specify criteria to give Pass/Warning/Fail of analysis setup and
results
- View-only Mode
- Open all available viewing tools to see analysis results without
using other licenses
- Support for CentOS/RHEL 5 and Windows 32-bit ends with next
release
- Library Support for Microsemi
- Page added to Design Settings
- New CDC Report
- Check-box added to Analysis Settings → Report Options
page
- GUI Updates
- Separation of Tutorials from Examples
- Enable new check-box on Settings → Preferences causes
Help menu to show Open Tutorial Project
- Loading of BPS file at startup now occurs after close of splash
screen
- New Tcl Variables page under Design Settings
- New Design Signoff page under Design Settings
- New check-boxes in Analysis Settings → CDC Options
page
- Choose whether to report Equivalent Clock CDCs (default is
off)
- Option for Max CDC Limit to apply only to CDC Viewer,
not messages
- Find CDCs from primary input and output ports
- The Analysis Settings → CDC → Endpoint Filters page
has been removed
- This functionality should now be handled using CDC waivers
- New default for -output command line option
- Default value is now ./bluepearl.results
- Was current working directory
- Obsolete and deprecated items
- Known Issues
- Platforms Supported
- Windows 7, 8.1 and 10, 64 bit and 32 bit
- CentOS/Red Hat Enterprise Linux 5.x and 6.x
- This will be the final release to
support CentOS/RHEL 5 and Windows 32-bit!
- New Messages
- BPS-0842 - Details of multiple top level entries
- BPS-0843 - Locations of multiple `define
entries
- BPS-0844 - Design Signoff Criterion has a TCL issue
List of Bugs
Fixed
- #2219 - Fixed issue when filtering info for large designs in
Analysis Report
- #2339 - Fixed issue when clicking faster than the GUI could
handle
- #2489 - Corrected misidentification of enable_clk inside a BUFGCE
as clock source
- #2507 - Suppress Equivalent Clock CDCs (see above)
- #2511 - Connect DI input and DO output in Xilinx library for
FIFO36
- #2512 - Add Xilinx UGC library Support for Xilinx FIFO36 and
FIFO18
- #2522 - Fixed issue with loading a bps project after the splash
screen
- #2526 - Enhanced support for Xilinx IDDR Cell
- #2527 - Enhanced support for Xilinx IDELAYE2 Cell
- #2534 - Fix for bad behavior opening files from
transcript
Blue Pearl Software Suite -- Release 2016.1
(2016.1.53924)
February 25, 2016
Return to Top
List of
Key Features
- Pivotal expansion and enhancement of the Tcl flow
- Full control of the tool is now possible via 100 additional new
Tcl commands
- The GUI now launches the core in Tcl command mode
- Non-Tcl flow is now deprecated
- New Tcl commands, options, and variables
- Replacements for old control file commands
- Most former arguments of BPS::set_options are now global
variables
- New Waivers Manager
- Allows creation and application of XML-format files for Message
and CDC waivers
- CDC Waivers apply to CDC Viewer only
- Message waivers can be Must-fix or Won't-fix
- Waivers can be enabled or disabled
- Waivers Manager can load and edit files containing either or both
CDC and Message waivers
- GUI Updates
- The GUI now produces the files
rootmodule.settings.tcl and
bluepearl.runme.tcl in place of the old deprecated
control files listed below
- Analysis Report filter tabs Modules,
Objects, Severities and Files now have buttons
for Check Selected, Uncheck Selected, and Uncheck All
- New command Design Settings → Add HDL Design Files into
Library
- Allows the user to directly declare an alternate library for new
HDL files
- User can specify Current Working Directory as the default design
directory
- Intended for Linux users who start the GUI from the command
line
- New page Design Settings → Block Labeling
- Allows control of labeling requirement for outermost and inner
level begin statements
- New page Design Settings → Tcl Files
- Allows the user to specify additional Tcl command files to
augment normal GUI functions
- New Check Names column in Analysis Report
window
- Lists all checks for the given message
- Significant improvement to Altera library support
- Users can add custom messages and message categories
- Tcl commands allow printing of your own conditional messages to
the message database and log file
- Library Mapping
- Create an alias for a hard-coded library name
- Allows the use of a single library without changing hard-coded
library names
- Available for both Verilog and VHDL
- New command line options
- -root is now the preferred alternative to -top,
which is now an alias
- -logfile - Specify log file name
- -outf - Specify name for writing effective command line
argument file
- -generate_project - Specify the name of a Tcl command output
file
- Facilitates conversion of deprecated control files to Tcl
equivalents
- Obsolete and deprecated items
- Old control files (*.inp, *.chk, *.cfg, *.atr, *.con) are
deprecated
- Relevant commands are now available through the Tcl interface
- These files are no longer produce by the GUI (see above)
- Numerous command line options are deprecated in favor of Tcl
equivalents
- Deprecated command line options now produce message BPS-0832
- Message BPS-0732 is deprecated
- Tcl command BPS::set_options is obsolete
- Analysis Settings → Clock Initialization page in GUI is
obsolete
- Checks MCKN and MRSTNAME are now obsolete and their functionality
is included in CCKN and RSTNAME, respectively
- Messages BPS-0672 thru BPS-0679 are obsolete and replaced by
BPS-0036, BPS-0038, and BPS-0571 thru BPS-0576
- New Release Numbering Scheme
- Major releases are now numbered by the year
- The first release of 2016 is now 2016.1 rather than 9.3
- New log file naming
- The default name for all log files is now
bluepearl.log rather than
rootmodule.log
- The user can use the -logfile option to specify a
different name
- Known Issues
- In order to see the new Check Names column in the
Analysis Report window, established Windows users may need to first
delete the registry folder:
- HKEY_CURRENT_USER\Software\Blue Pearl Software, Inc\Blue Pearl
Visual Verification Environment\CReportView
- Platforms Supported
- Windows 7, 8.1 and 10, 64 bit and 32 bit
- CentOS/Red Hat Enterprise Linux 5.x and 6.x
- New Checks
- REGO_SYNCH - Ensure that output is double-registered
- REGI_SYNCH - Ensure that input is double-regestered
- MISALIGNED_CYCLIC_SIGNALS -Report on misaligned cyclic
signals
- CONDITIONAL_HOLD_ONLY - Report on conditional constructs that
only hold value
- MISSING_DEFINITION - Report variables, functions, or tasks that
have no definition
- PARAM_SIZE_OVERFLOW - Report parameters requiring more than 32
bits
- EVENTLIST_CONSTANT - Report constant event lists
- DUPLICATE_IDENTIFIERS - Identifiers differ only by case
- FORLOOP_ITER_NONINT - For-loop with non-integer iterator
- ACCESS_GLOBAL_VAR - Variable or net accessed globally
- UNLOADED_SEQ - Report on sequential elements that drive unloaded
logic
- New Check Options
- Check MBA now has option to exclude type mismatches (e.g. integer
vs vector)
- Check MEA now has option to report missing else assignments for
extant else blocks, even if no latch is inferred
- New Messages
- BPS-0819 - Specified signal is used here before it is
assigned.
- BPS-0820 - Specified variable is used here before it is
assigned.
- BPS-0821 - Explicit list of multiple top modules is now under
message system control
- BPS-0822 - Notification of top level module auto-selected from
multiple choices
- BPS-0823 - Option requires floating point argument
- BPS-0824 - Option requires one and only one argument
- BPS-0825 - Programmable clock found
- BPS-0826 - Output is not double-registered
- BPS-0827 - Input is not double-registered
- BPS-0828 - Misaligned cyclic signals
- BPS-0829 - Inputs not controlled by aligned cyclic
signal
- BPS-0830 - Conditional Hold Only
- BPS-0831 - Missing Definition
- BPS-0832 - Deprecated command line option
- BPS-0833 - Constraint clock not found
- BPS-0834 - Constraint port not found
- BPS-0835 - Cannot generate project file
- BPS-0836 - Parameter size overflow
- BPS-0837 - Constant event list
- BPS-0838 - Identifiers differ only by case
- BPS-0839 - For-loop with non-integer iterator
- BPS-0840 - Variable or net accessed globally
- BPS-0841 - Report on sequential elements that drive unloaded
logic
List of Bugs
Fixed
- #1404 - Added MISSING_DEFINITION check and message
BPS-0831
- #2156 - Fix for failure to identify a style of state machine
coding
- #2328 - Nested 'begin' statements in generate blocks can be left
unlabeled
- #2415 - Fix for Duplicate Case items greater than 128
bits
- #2419 - Registers with no load other than feeback are now marked
as unloaded
- #2423 - Added CONDITIONAL_HOLD_ONLY check and message
BPS-0830
- #2425 - Used Before Assigned now indicates both Used and Assigned
locations
- #2426 - Added option mea_report_missing_else_only to MEA
check
- #2428 - Added checks REGO_SYNCH and REGI_SYNCH
- #2432 - Fix for mismatching bit ranges right hand side reported
as 1-bit
- #2433 - Check MBA now has option to exclude type mismatches (e.g.
integer vs vector)
- #2434 - Support for library mapping
- #2435 - Fix for single indexed array defintion
- #2436 - Messages on objects without line/file info now point to
their parents' line file info
- #2437 - Analysis report now shows messages that lack line file
info
- #2438 - Expanded capability of check MBA to recognize multi-step
arithmetic operations
- #2439 - Allow design loading when submodule has
error
- #2440 - Mismatch bit width now properly handles part select
operator (+:)
- #2441 - Message VHDL-1544 is now a Warning under Language
Checking Level "relaxed" (still an error under "default")
- #2448 - Improved coverage of FSMs, counters, and other elements
not in root library
- #2449 - Fixed problem in staged reset analysis
- #2451 - Fixed issue found during Running dynamic property
checks
- #2453 - Fix for ternary operator reporting mismatching bit
ranges
- #2455 - Added ACCESS_GLOBAL_VAR check and message
BPS-0840
- #2456 - Added EVENTLIST_CONSTANT check and message
BPS-0837
- #2459 - Added DUPLICATE_IDENTIFIERS check and message
BPS-0838
- #2464 - Added PARAM_SIZE_OVERFLOW check and message
BPS-0836
- #2466 - Added FORLOOP_ITER_NONINT check and message
BPS-0839
- #2457 - Fix for labeled subprogram calls in VHDL
- #2461 - Fixed mismatching bit range for assignment messages on
multiple additions
- #2481 - Altera model updated for missing pin
eccstatus
- #2484 - Analysis Report filter tabs now have more control
buttons
- #2485 - Sorting is now maintained when copying from Analysis
Report results
- #2498 - Fixed waiver summary in Analysis Report HTML
output
Blue Pearl Software Suite -- Release 9.2 (9.2.33245)
September 29, 2015
List of Key
Features
- Updated Xilinx Libraries
- Support for Vivado 2015.2
- Support for retarget cells
- More Verific messages
- Duplicate Verific (ELAB, VERI, VHDL) messages are no longer
deleted
- New VSRT message set to document auto-sorting of VHDL
files
- New Text Report
- SLOC: Number of lines of code in each source file
- New Tcl Options and Commands
- Access to result runs is now available from the Tcl interface.
New BPS:: commands include
- get_message_count
- get_result_runs
- name_result_runs
- get_result_run_message
- get_result_run_summary
- result_run_compare
- Check INDENT_TABS has a slight behavior change
- Now flags an otherwise blank line with only spaces
- New Messages
- VHDL-9004 - Duplicate primary unit ignored
- VHDL-9005 - Duplicate secondary unit ignored
- VHDL-9006 - Location of duplicate unit
- VSRT-1001-1011 - VHDL File Sorting Messages
- VSRT-9000 - Information message regarding pre-analysis of VHDL
file
- BPS-0816 - Potential Multi-cycle Path is actually a False
Path
- BPS-0817 - Construct is deprecated in upcoming language
version
- BPS-0818 - Vectored net identified as clock
- GUI Updates
- New options for Active Low Naming (ALN) top level ports and
internal nets are now on the Design Settings → Net Options
page
- New options for Reset Signal Naming (RSTNAME and MRSTNAME) top
level ports and internal nets are now on the Design Settings →
Net Options page
- The sole item on the Analysis Settings → Naming page
has been moved to the Design Settings → Naming page
- SystemVerilog files now have proper highlights in the default
editor
- Current Design link on the main page has expanded
functionality
- New check-box on Design Settings → Assignments page
for Include Default Case blocks for PREV_ASSIGN check
- Obsolete and deprecated items
- The Analysis Settings → Naming page in the GUI is
gone
- Known Issues
- Platforms Supported
- Windows 7, 8.1 and 10, 64 bit and 32 bit
- CentOS/Red Hat Enterprise Linux 5.x and 6.x
List of Bugs
Fixed
- #2327 - Report the use of deprecated language
constructs
- #2363 - Better support for bused clocks
- #2372 - Fixed inability to disable Automatic Clock
Detection
- #2374 - Fixed issue with VHDL alias bit-width
checking
- #2375 - Fixed issue with VHDL records bit-width
checking
- #2376 - Fixed documentation issue causing misunderstanding of UNO
check
- #2377 - Fixed incorrect marking of root module causing REGI and
REGO failures
- #2379 - Better detection of staged resets
- #2380 - Added architecture to VHDL FSM report
- #2382 - Fix for CDC filters issue
- #2383 - Fixed CDC schematic bug for nets that also drive output
ports
- #2384 - Expanded capability of check ALN for naming of negative
clk/rst signals
- #2383 - Certain CDC schematics are no longer
incomplete
- #2388 - Fix for BPS-0684 issue on Windows
- #2393 - Fixed bug in disabled messages via
pragmas being counted toward filtering
- #2411 - VHDL syntax A to B and A downto
B case alternatives in a state machine are now
supported
- #2412 - VHDL timing syntax after is now
supported
- #2413 - Mismatch bit width check now properly handles user
defined type
- #2414 - Underscore is no longer considered a word delimiter in
the editor when searching for whole words
- #2417 - In the GUI, System Verilog files are now highlighted
properly
- #2420 - Fixed bit width calculation using clog2
- #2422 - Check PREV_ASSIGN now has DEFAULT_INCLUDED_PREV_ASSIGN
option
- #2424 - Support for retarget cells for Xilinx
Blue Pearl Software Suite -- Release 9.1 (9.1.31725)
July 1, 2015
List of Key
Features
- New Live Log File feature makes log file a debugging
tool
- Rollover text and RMB menu choices now available from main window
log
- Rollover text appears when cursor is on any object name
- RMB on object name provides access to object-specific commands,
including schematic, HDL file, and cross-probe
- New Multi-trace Technology
- Display trace schematics from any pin or net in the design to any
driving or loading register or port in its logic cone
- Available from all viewer tools, report tools, and the log
file
- New Critical Path Report View
- Use the Path Viewer to display critial timing paths from Altera
or Xilinx
- Reduced Memory Footprint
- Internal improvements have reduced the Blue Pearl Software
Suite's memory footprint by 30% or more
- Analysis Report Filter improvements
- Tabs with lists now include message counts
- Tabs for Objects and Modules include rollover and RMB
commands
- Message text is now "live" with rollover and RMB
commands
- RMB commands for appropriate messages include access to CDC or
False/MC Path Viewer
- RMB on specific messages opens relevant viewer
- RMB on BPS-0314 False Path opens that path in
False/Multi-cycle Path Viewer
- RMB on BPS-0315 Multi-cycle Path opens that path in
False/Multi-cycle Path Viewer
- RMB on BPS-0281 and other CDC messages opens that path
in the CDC Viewer
- Improved Design Browser
- Design Browser now accesses schematic, HDL files, cross-probing,
etc.
- New Searchable stand-alone design browser
- Expanded cross-probing between tools
- Cross-probing between tools now occurs on RMB command rather than
automatically
- Command is issued from the Select Item
Actiontoolbar
- Cross-probing is now expanded to include False Path, CDC, and
Path Analysis viewers
- Improvements to User Grey Cells
- VHDL issue regarding black boxes is addressed
- Enhancements to User Grey Cell flow
- False Path Schematics are cleaner
- Large text notations on nets have been replaced with a question
mark
- Previous information is available via rollover on the question
mark
- All trace schematics are less cluttered
- Unconnected pins are no longer visible on user modules
- Fixed issue with properly determining VHDL top
module
- Adjustable schematic trace interrupt
- To avoid excessive delays in schematic tracing, the trace will be
interrupted after a number of seconds (default: 10) that can be
adjusted from the Settings → Preferences → Schematics menu
page.
- Additional flexibility for sub-windows
- Sub windows can now be made either dockable or
independent
- In dockable mode, sub-windows are constrained to be on top of the
main window
- The Analysis Report Filter is now treated in the same
way. It can be dockable or independent
- Other GUI improvements
- Analysis Report window saves sub-window sizes and report column
sizes and locations
- Scroll bars have been added to the Analysis Report's External
Filter to allow a smaller minimum size
- The Analyze license, if present, is now checked out by default,
and the the check-box on the Settings → Preferences menu
which controls this function is on by default
- Main Window now has Quick Search feature for log, with Next
Waring, Next Error, and a text entry area
- Main Window's Design Browser has new Show Root Module only
option, on by default
- The Auto-sort VHDL feature is now on by default
- There is now a Licenses page in both the Design Settings
and Analysis Settings dialogs to facilitate license enabling without
closing and reopening those dialogs
- New check-box to hide unlicensed checks on Load Checks and
Analysis Checks pages
- Rollover text indicates that grayed-out packages/checks require
an additional license
- Schematic display has been improved for modules with
parameterized names
- Schematics now have an optional labeled border, or label alone,
for printing
- New Trace Results sub-window in Schematic Viewer and other
schematic-based tools
- Improved interface to the Licensing Wizard
- Preferences function Clear Acknowledgement dialog disable
check boxes? is now a Clear button instead of a
check-box
- New Checks
- UNCONNECTED_UNDRIVEN_UNUSED_PIN - Report hierarchical instance
pins that are undriven and unused
- UNCONNECTED_UNDRIVEN_UNUSED_NET - Report signals that are
undriven and unused
- UNCONNECTED_UNDRIVEN_USED_PIN - Report hierarchical instance pins
that are undriven and used
- UNCONNECTED_UNDRIVEN_USED_NET - Report signals that are undriven
and used
- UNCONNECTED_DRIVEN_UNUSED_PIN - Report hierarchical instance pins
that are driven but unused
- UNCONNECTED_DRIVEN_UNUSED_NET - Report signals that are driven
but unused
- MCKN - Consistent Clock Names from User Settings
- MRSTNAME - Reset Names from User Settings
- RST_MULT - Report reset signal used as multiple types of reset
signal, e.g. synch and asych or set and preset
- SET_RESET_UNCONNECTED - Report unconnected set or reset signal on
DFF
- RST_INTERNAL - Report the use of internal set/reset
signals
- ICKGT - Report internally generated gated clocks
- UNDCLK - Report on undriven internal clocks
- BBCK - Report clocks driven by black boxes
- CLK_BUS - Report bused clocks
- Subdivided checks that produced too many messages
- Four of eight messages produced by check CCKN moved to new
check
- Four of eight messages produced by check RSTNAME moved to new
check
- Eight of twelve messages produced by SYNCH_SR moved to new and
existing checks
- Fourteen of twenty-three messages produced by IGCK moved to new
and existing checks, and one other (BPS-0114) is now a system message
- New Messages
- BPS-0801 - The specified signal is undriven but is used in the
design
- BPS-0802 - The specified signal is used but has no driver
- BPS-0803 - The specified pin is undriven but is used in the
design
- BPS-0804 - The specified signal is undriven but is never used in
the design
- BPS-0805 - The specified signal is dangling but has no drivers
- BPS-0806 - The specified pin is undriven but is never used in the
design
- BPS-0807 - The specified pin is dangling but has no drivers
- BPS-0808 - The specified signal is undriven but is never used in
the design
- BPS-0809 - The specified signal is dangling but has no drivers
- BPS-0810 - The specified pin is dangling but has drivers
- BPS-0812 - A `celldefine has no matching `endcelldefine in the
same file
- Obsolete and deprecated items
- The report constant_nets configuration and command line
option are no longer available. The functionality of this
report has been improved and is now included in the Nets
report
- The message BPS-0110 - Equivalent of "Cannot find module" is
gone: this function is now handled differently
- Known issues
- Waivers are currently tied to the text of the specified message,
therefore changes that have been made to the text of some
messages may interfere with the function of some existing waivers
files
- Platforms Supported
- New: Windows 8.1, 64-bit
- Windows 8.1, 32-bit
- Windows 7, 64-bit
- Windows 7, 32-bit
- Linux Red Hat Enterprise v.5
- Linux Red Hat Enterprise v.6
- Linux CentOS 5.x
- Linux CentOS 6.x
List of Bugs
Fixed
- #2083 - Fixed ungrouped checks display in Design Settings →
Load Checks and Analysis Settings → Analysis Checks
- #2274 - Fixed LHS width mismatch in VHDL
- #2277 - Fixed issue with automatic clock detection
- #2309 - Support for unknown and undefined components with User
Grey Cells
- #2320 - Fixed improper if-then-else message for VHDL
- #2321 - Fixed improper mismatching bits messages for
VHDL
- #2322 - Fixed improper Verilog-only notation on BPS-0565
message
- #2323 - More appropriate message for VHDL arithmetic overflow
case
- #2324 - VHDL port and net comments are now properly
recognized
- #2333 - Fixed issue with Report Module Usage
- #2338 - Improved cross-probing from objects defined in generate
statements
- #2344 - Support for FSMs with constants as state values in
VHDL
- #2352 - Fixed Exclude Arithmetic: MBA for nested ternary
operators
- #2358 - Updated FPGA libraries to fix clock recognition issue for
MMCM
Blue Pearl Software Suite -- Release 9.0 (9.0.29254)
March 23, 2015
List of Key
Features
- 64-bit Windows
- There is now a 64-bit version of the Windows
build
- Disabled Code is now highlighted in report and HDL
viewer
- New Disabled Code report outlines code that is
inactivated by constructs such as ifdef, ifndef, or
translate off
- Such code now appears gray in the HDL viewer
- HDL File Line-based message access
- HDL Viewer indicates code lines flagged by
messages
- Text of messages available via roll-over when cursor is on
left-hand severity indicator
- Roll-over text is sensitive to cursor location within the line,
and provides file locations and, where applicable, clock domain and
connection information for the object indicated by the cursor
- RMB from any line in any HDL View window opens Analysis Report
for pertinent messages
- Analysis Report filter for Files now has Start Line and End Line
parameter for each file
- Command line help system
- Users can now enter e.g. BluePearlCLI -help
BPS-0123 or BluePearlCLI -help meb
- Help for messages is case-sensitive, help for checks is
not
- Tcl help system
- Entering help [string]at Tcl prompt matches all
available help topics
- Using help [string] -type
[Commands|Messages|Checks|Packages|Extras] to narrow choices to one
possibility can display the same help text files as are available from
the command line
- Command line option -licensing_help now always opens
licensing wizard
- Previously opened wizard only if a problem was
detected
- Counters Report now available from Text Reports window
- Activate from Design Settings → Reports menu
- Other report improvements
- The DFFs, Latches, Ports, and
Nets text reports now include appropriate clock domain
information
- The Module Usage report has added data on where and how
many times a module is instantiated, now includes a table view, and has
droped the unused module list
- Schematic Viewer Enhancements
- New Design Browser check-boxes for
disabling/enabling Enable Object Cross Probing and Zoom
to Object in Schematic on Selection
- New context-sensitive Selected Item Action Toolbar will
change based on which object is selected
- Enhanced roll-over text for schematic elements included
connections and clock domains where appropriate
- The highlight feature (for a net) crosses a single level
of hierarchy, which allows the user to Unfold a submodule and
retain the highlight, or Unfold a module and see where the
signal came from in the next level up. Note that this does not apply
to Hierarchy Up/Down.
- Tracing has been enhanced beyond tracing to the next logic
element to include tracing forward and backward for logic
cones.
- Design Operations File functions are no longer
available
- Pages deleted from the Analysis Settings dialog include
the Initializations, Visible Registers, Scan Chains, and
Test Procedures pages
- The Clock Initialization page has moved under Check
Options
- New Database Search function
- Direct search of design database
- Access from Main Window using Design Verification
menu from RMB on Design Browser
- The main window Design Browser support RMB access to schematics
and database search
- The GUI's Open Design function now supports -f files in
addition to .bps and .inp
- Improved License Wizard user interface
- Window installation now uses a .exe file instead of a .msi
file
- Window XP is no longer supported
- The .des file is no longer supported
- The packages Scan DFT and Non-scan DFT have
been consolidated into one package called DFT
- SuSE SLES 11.2 and SLES 10.3 are no longer directly
supported
- Obsolete Checks
- SCAN
- DFT_SR_INACTIVE
- CAPTURE_CLK
- LTH_TRANS
- RST_SAME_CLK_EDGES (grandfathered in until next release)
- RST_DIFF_CLK_EDGES (grandfathered in until next release)
- Obsolete Messages
- BPS-0205
- BPS-0231 thru BPS-0235
- BPS-0241
- BPS-0417
- New Checks
- REPORT_DFFINFO - Add information on counters to the DFF
report
- RST_CLK_EDGES - Combines the functionality of RST_DIFF_CLK_EDGES
and RST_SAME_CLK_EDGES
- New Messages
- BPS-0790 - Report the presence of a counter
- BPS-0791 - Note that a reported counter has nothing to prevent a
wrap-around from maximum to minimum count or vice-versa
- BPS-0792 - Report possible User Grey Cell
- BPS-0793 thru BPS-0795: Path Error messages
- BPS-0796 - Flow debugging message
- BPS-0797 - Filter point path not found
- BPS-0798 - Filter point element not found
- BPS-0799 - Extracting Grey Cell from indicated module
- BPS-0800 - Summary of extracted Grey Cell results
List of Bugs
Fixed
- #1603 - Avoiding use of internally-generated net names in
messages
- #2110 - Improved recognition of negative assignments in
SystemVerilog
- #2263 - MCP issue for a different style of writing
- #2267 - Enhanced classification of CDCs as
synchronized
- #2274 - Fixed improper expression size calculation in
VHDL
- #2285 - Use the unparamaterized name when creating User Grey
Cells in VHDL
- #2286 - Fixed mismatching bit assignment issue in
SystemVerilog
- #2287 - Reports from Advanced Clock Analysis are now more
consistent with CDC results
- #2289 - Improved support for BUFR Xilinx primitive
- #2290 - Support for Xilinx CLKDLL clock generation
primitive
- #2295 - Prevent loading of the design if current design is not
set
- #2299 - Extraneous messages in VHDL regarding missing if
assignments have been eliminated
- #2300 - Fixed VHDL issue for muliple entiy messages
- #2307 - Improved handling of parameterized User Grey Cells in
VHDL
- #2311 - Improved VHDL Autosort
Blue Pearl Software Suite -- Release 8.3 (Build 8.3.25969)
October 23, 2014
List
of Key Features
- User Grey Cell Editor
- Assists users in specifying or modifying User Grey
Cells
- Strict message mode
- The messaging system now has a Strict mode to
complement the Relaxed mode
- The Design Settings→Messages page has radio buttons
for Default, Strict and Relaxedin place of
the Relaxed mode check-box
- Expanded control of reset analysis
- Option to enable automatic preset/clear detection via
latches
- Option to enable inclusion of asynchronous set/reset
with analysis of synchronous set/reset
- Option to allow internally gated signals to be reported as
primary synchronous resets
- Option to allow mux select signals to be reported as primary
synchronous resets
- Option to report constant driven muxes driving DFFs to be
considered as synchronous resets (default on)
- Options for reporting of staged resets (All, Asynch Only, Synch
Only, None)
- Options for reporting of synchronous resets (All, Primary only,
matching by name only)
- Licensing Wizard
- Assists new users in requesting and installing license
files
- Can be run from Help menu
- Check for Latest Version feature alerts the user to
available updates
- Can be run from Help menu
- Automatic launching can be controlled from the Preferences
page
- Improved algorithm for auto detection of reset signals
- Change in counting of combinational levels
- The counting of combinational logic levels now uses
weighted values for elements such as comparitors, multipliers,
reduction OR gates, and case statements. This more closely matches
results from optimized synthesis.
- Inverters are now treated the same as buffers in that they are
not counted.
- This affects the COMB_LEVELS check and the Path Analysis
Viewer.
- Configuration command change
- The configuration file command tcg_effort is now
path_analysis_effort and the available arguments are now
low, medium, high and maximum
- New Command Line Options
- -check_for_latest_version displays latest version from
Blue Pearl Software's servers. There is a verbose option
(default off) that displays full release notes for each
version
- -licensing_help option runs Licensing Wizard
- Format of -help option output has been improved
- Obsolete Command Line Options
- Options for path analysis have moved to the
configuration file: -enable_path_analysisis now cfg command
path_analysis enabled,
-num_{dff,port}_to_{dff,port}_paths options are now
path_analysis num_{dff,port}_to_{dff,port}_paths
- There is a new cfg command path_analysis all_paths_on
- GUI Changes
- There is now a fourth radio button under Check Design →
Analysis Settings → MCP Analysis Options → Create Multi-cycle path
-setup and -hold based exceptionsthat enables the default value of
#cycles - 1
- The FP and MCP Analysis Options page now has a pull-down
for setting Path Analysis Effort level to Low, Medium, High,
or Maximum, where each level enables a recommended set of options for
analyzing paths and thus finding more false or multi-cycle
paths
- The Settings→Preferences page now has a new checkbox,
on by default, to enable or disable the feature
-check_for_latest_version described above
- The Settings→Preferences page has a new License
Location entry that shows the location of the license file or the
value of the link
- Help menu provides access to -check_for_latest_version
feature, licensing wizard and Blue Pearl's licensing web
page
- New check-box on Analysis Settings → Path Analysis Options
for Display all paths between start and end points
- New Checks
- TEST_POSEDGE - New check added to control pre-existing message
BPS-0229
- TEST_NEGEDGE - New check added to control pre-existing message
BPS-0230
- REPORT_PARAMS_MISMATCH - Report on instantiations with a
mismatched number of parameters (formerly controlled by REPORT_PARAMS)
- REPORT_PARAMS_MOD_NAME_TOO_LONG - Report on instantiations with
excessively long generated names (formerly controlled by
REPORT_PARAMS)
- REPORT_PARAMS_OVERRIDDEN - Report on non-default parameter values
(formerly controlled by REPORT_PARAMS)
- REPORT_PARAMS_RANGE_MISMATCH - Report on parameters with an
assigned range that is exceeded (formerly controlled by
REPORT_PARAMS)
- REPORT_MODULE_CONSTANTS - Report on constants defined in a
module
- REPORT_VHDL_DATAFLOW_ON_RANGE_ERROR - Report value state on VHDL
range error
- New Messages
- BPS-0782 - Multi-cycle path with setup time specified
- BPS-0783 - Multi-cycle path with hold time specified
- BPS-0784 - Report on constants defined in a module
- BPS-0785 - When reporting on parameters, this message is a
placeholder for modules with no parameters
- BPS-0786 - When reporting on unused parameters, this message is a
placeholder for modules with no parameters
- BPS-0787 - Reports the existence of a VHDL range error
- BPS-0788 - Reports the details of a VHDL range error
- BPS-0789 - Warning on UGC file format
- ELAB-9003 - Multiply driven user net removed
List of
Bugs Fixed
- #2235 - Improved handling of variables in
elaboration
- #2244 - Fixed clock analysis for PLL driven by user-specified
clock
- #2251 - Enhanced ease of diagnosing index out of array messages
Blue Pearl Software Suite -- Release 8.2 (Build 8.2.24639)
August 7, 2014
List
of Key Features
- New Product - Advanced Clock Environment (ACE)
- Load only - no analysis
- No checks
- Provides a graphical representation of clocks and clock
domains
- Provides recommendation for grouping clocks into domains
- Used before running CDC analysis
- GUI Changes
- New check-box on Preferences dialog to always check out
Analyze license if available
- New ACE License button
- Check Out License button has been removed from Design
Settings → Clocks page
- Access to the New Design Wizard has moved from the
Scenarios pull-down to the Setup Design
pull-down
- The check-boxes Convert Gates to Muxes and Always
load the design from source during analysis have moved from
Design Settings → Design Files to Design Settings →
General
- Default column locations in Analysis Report window have
changed
- Analysis Settings → Path Analysis Options → Constants File
has been removed
- Green Triangle (5th) Tool Bar shortcut loads the design if no
Analysis license is checked out
- The Design Settings → Design Files page allows
disabling of "translate off" either globally or on a file-by-file
basis
- New Report
- Gated Clocks are now have a separate report and are removed from
the Clocks report
- The appropriate additions appear on the reports enabling dialog,
the ouptut window and the command line option
- Option Removed
- The option -path_analysis_constants_file has been
deprecated: use Design Settings → Signal Constraints
instead
- New command line option
- -disable_translate_off will disable translate_off for
all input files
- Check Renamed
- Check Removed
- Messages Removed
- New Checks
- New Messages
- BPS-0773 - Problem saving BPS VDB File
- BPS-0774-777 - Bit length mismatch on mux inputs
- BPS-0778-779 - Asynchronous reset to non-constant
- BPS-0780-781 - Ambiguous logical or reduction operator
List of
Bugs Fixed
- #2206 - Add check for ternary operator bit width mismatch
(MOS_TERNARY)
- #2210, #2211 - More consistent display of clock domains in CDC
Viewer
- #2214 - Added check for ambiguous logical or reduction operator
(PAREN_UNARY)
- #2216, #2229 - Recognize more FSM configurations
- #2222 - Enhanced recognition of bused clocks from Altera
PLL
- #2227 - Warning if asynchronous reset to
non-constant
- #2233, 2234 - Fixed deriving of clocks from Xilinx MMCM_ADV and
MMCMED_ADV blocks
Blue Pearl Software Suite -- Release 8.1 (Build
8.1.23971)
June 14, 2014
List
of Key Features
- Design setup wizard
- Helps set up design projects, design scenarios, and analysis
scenarios
- Saves design scenarios and analysis scenarios for
re-use, even with other designs
- Multi-cycle path schematics
- You can now view schematics for multi-cycle paths in the False
and Multi-cycle Path Viewer
- New Clock Interaction Viewer
- Simple graphical representation of clock-to-clock pathways
- Path Schematic Viewing
- You can now view path schematics for selected messages
- Enable path schematics on a per-message basis from Design
Settings → Messages
- Access path schematics from log file display or Anaysis
Reportwindow
- Clock domain enhancements
- Automatically re-define clock domains based on clock
interactions
- Numerous clock and reset messages are now generated earlier in
the flow
- Header-only SDC files will no longer be generated
- Better support for RAM inferencing
- Specify in new Design Settingspage RAM Inferencing
Analysis:
- Maximum RAM bit size to avoid excess run time
- Minimum bit size above which 2D arrays will be implemented as
RAMs
- Maximum RAM bit size at which any specified initialization values
will be preserved
- New RAM text report
- Greater specificity in Xilinx library selection
- User can specify Virtex 6 and older, or Virtex 7, or only 'glbl'
module
- We have added UniMacro support for both Virtex libraries
- Select these from the Design Settings → FPGA Vendor
Options → Xilinx Optionspage
- Streamlined list of default checks
- Default checks are collected into a new package called Basic
Checks
- Enhanced report generation
- New reports available
- All "report" functions now generate .rpt file
- Those that did not are moved to new Log File Options,
chkoptions or sdc_file writefunctions
- cfg file entry report
cdc_from_static_control_registers is now chk_option
CDC_ON_STATIC_CONTROL_REGISTERS (now on Analysis Settings
→ Clock Domain Crossings Options page in GUI)
- cfg file entry report constant_phase_cdc is now
chk_option CONSTANT_PHASE_CDC
[ALL|FREQ_IS_MULTIPLES|FREQ_IS_SAME] (now onAnalysis
Settings → Clock Domain Crossings Options page in GUI)
- cfg file entry report mcp_setup_and_hold is now
sdc_file write mcp_setup_and_hold [on|off] (still on
Analysis Settings → MCP Analysis Options page in
GUI)
- New Design Settings page: Log File Options
- All functions augment log file
- Some functions (e.g. Maximum Message Limit) moved from General
Options to Log File Options
- New Maximum Message Storage Limit
- Per-message limit on writing to database (default 10,000)
- New Analysis Settings pages
- FP and MCP Endpoint Filter Options
- Also allows the loading of STA results from Altera or Xilinx
- Clock Domain Crossing Options → Endpoint Filters
- Formerly Check Options → End Point Filters
- Report Options
- Analysis-related reports no longer appear on the Design Settings
page
- NewAnalysis Settings → FP and MCP Analysis Options
commands
- Assume reset only at initialization?
- .cfg file option analysis
assume_reset_only_at_initialization
- Assume state retention clock gating?
- .cfg file option analysis
assum_state_retention_clock_gating
- New Analysis Settings → Clock Domain Crossing Options
commands
- Assume only one muxed clock can be active at a time?
- .cfg file command analysis assume_one_muxed_clock_active
(formerly analysis multimode)
- Treat the output of muxed clocks as an internal clock?
- .cfg file command analysis
output_of_muxed_clock_as_internal_clock (formerly analysis
internal_clock_domains)
- All references to DOUBLE_BUF and double buffer
wrt CDCs changed to DOUBLE_REG and double
register
- Check REPORT_ON_DOUBLE_BUF_SYNCHis now
REPORT_ON_DOUBLE_REG_SYNCH
- Check REPORT_ON_GRAY_CODE_ DOUBLE_BUF_SYNCHis now
REPORT_ON_GRAY_CODE_DOUBLE_REG_SYNCH
- Some attribute (.atr) file directives no longer
supported
- Primitive
- File filtering
- Analog
- Some configuration (.cfg) file commands no longer
supported
- analysis no_state_retention_on_startpoints
- analysis no_state_retention_on_start_points
- analysis mcp_data_constraints
- analysis relaxed_mcp_data_constraints
- analysis constant_propagation
- analysis skip_full_case_learning
- analysis mcp_staged_control
- analysis start_point_transitions
- analysis reachability
- analysis state_justification
- analysis sequential
- analysis net_splices
- analysis heuristically_block_trace
- analysis dynamic
- analysis static
- analysis vectorless
- analysis clock_gating
- analysis auto_decompose
- Some configuration (.cfg) file commands
re-named
- All commands containing strings startpointsand
endpointsare now start_pointsand end_points
- Both options used to be valid, but no longer
- New Diagnostic Options pages on both Design Settings and Analysis
Settings dialogs
- Intended to assist Blue Pearl in solving customer issues with
minimal resources from either side
- Long list of check-boxes, sparsely documented, subject to change
without notice
- Redundant command line options removed
- -prop_fileand -aux_check_filenow replaced by extant
option -chk_file
- Multiple -chk_fileoptions allowed
- New Checks
- REPORT_ON_SYNCH_USER_GREY_CELL
- CLOCK_RECOMMENDATIONS
- New Messages
- BPS-0744 - Analyzing all paths from point (followed by a series
of BPS-0747 messages)
- BPS-0745 - Analyzing all paths from point to point (followed by a
series of BPS-0747 messages)
- BPS-0746 - Analyzing all paths to point (followed by a series of
BPS-0747 messages)
- BPS-0747 - Detailed path information
- BPS-0748 - Invalid argument for -log option
- BPS-0749 - Potential path information, from - to
- BPS-0750 - Potential path information, from
- BPS-0751 - Potential path information, to
- BPS-0752 - Flow status error
- BPS-0753 - Flow status warning
- BPS-0754 - Unsensitizable path
- BPS-0755 - Clock synchronized by User Grey Cell
- BPS-0756 - Unable to draw schematic for a given path
- BPS-0757 - Derived clock put in separate domain
- BPS-0758 - Equivalent clock was not auto-detected
- BPS-0759 - Mixed synchronization interactions
- BPS-0760 - Too many mixed synch interactions between
domains
- BPS-0761 - Too many auto-mixed synch interactions between
domains
- BPS-0762 - Mixed synch interactions between domains
- BPS-0763 - Mixed synch interactions within domain
- BPS-0764 - Synched CDCs in same domain
- BPS-0765 - Unsynched CDCs between domains
- BPS-0766 - Clock pin was mapped
- BPS-0767 - Equivalent clock was read from net
- BPS-0768 - Unable to map clock
- BPS-0769 - Clock from group was re-mapped
- BPS-0770 - Clock specified in multiple groups
- BPS-0771 - Ignored duplicage equivalent clock
- BPS-0772 - Mapped clock to group
List of
Bugs Fixed
- #2075 - Display example clock-to-clock false path schematic, if
available
- #2175 - Improved reporting of CDCs w/ synchronous
resets
- #2155 - Support for User Grey Cell (UGC) synch cells
- #2191 - No longer display waived messages
- #2194 - Fix for module attributes on vhdl designs with
generics
- #2199 - Fixed issue with dangling net message
Blue Pearl Software Suite -- Release 7.3 (Build 7.3.22590)
March 28, 2014
List
of Key Features
- Enhanced SystemVerilog compilation unit capability
- Directly control which files are grouped while compiling
- Expanded Example Projects
- Specify default directory in Preferences dialog
- No longer possible to run examples in the installation
directory
- Design-specific help file appears in Helpmenu after
example is loaded
- New Examples:
- Property Check: Reconvergence
- False Path: Complex
- False Path: Counter and arithmetic decode
- False Path: Counter and gate decode
- False Path: Constant Controlled
- False Path: For Resets
- False Path: Multi Cycle
- False Path: Clock to Clock
- False Path: Mode Based
- Multi-Cycle Path: Cyclic Analysis
- Multi-Cycle Path: Path Through Control
- Multi-Cycle Path: Finite State Machine
- Grey Cell: Declared
- Grey Cell: User Scalar
- Grey Cell: User
- Grey Cell: Xilinx FIFO
- Grey Cell: Altera FIFO
- Xilinx UltraFast Design Methodology
- Example labeled "Getting Started" has been removed
- Changes to Analysis Settings and Design
Settings pages in GUI
- FP and MCP Analysis Optionspage broken into three pages
- FP and MCP Analysis Options has options relevant to both
FP and MCP
- FP Analysis Options has options relevant to FP only
- MCP Analysis Options has options relevant to MCP
only
- Cyclic Signals page is now a child page ofMCP
Analysis Options page
- SDC Optionspage broken into two pages to accomodate three more
check-boxes
- Choices on Assignmentsand Namingpages are now
enabled by the appropriate checks
- Notations added to other pages regarding appropriate check
requirements
- Size Conflict Exclusion Optionspage has been simplified
- File extentions controls added to Design Settings →
Language
- New option to enable or disable detection of FSM-based
MCPs
- Analysis Settings and Design Settingsdialogs re-open on
last open page until tool is re-started
- More flexible sizing of dialog boxes
- Scroll bars available
- Better accommodates smaller screens
- Enhancements to Report Comparison
- New Report Summary Comparison window
- Filter by Severity available on Report Comparison and Report
Summary Comparison
- Analysis Report Window improvement
- Choose whether to have filter control integrated into Analysis
Report window or open as a separate window
- Default view no longer includes Comments
- Use RMB to copy selected message(s) to clipboard in CSV or Excel
format
- Improved Liberty cell support
- Support for port bundles
- Proper support for spaces in equations
- FSM License button is gone
- FSM License still exists
- Always shipped and activated with Analysis license
- New module library search path
- Specify search path for module libraries
- Primarily intended for mixed-language designs
- GUI: Design Settings → HDL Libraries
- CLI: -L option
- CDC Enhancements
- CDC Waivers now support wildcards
- Shift-register style synchronizers are now recognized
- Proper reporting of user synch cells in CDC Viewer
- Double-FF synchronizers properly supported in generated grey
cells
- Multi-language designs now require an explicit top module
declaration
- Tool ensures that settings location has write
permission
- Vendor libraries now include more User Grey Cells
- Better handling of cross-probing to networked source
files
- Enhanced handling of user mode-based constants in path
analysis
- Setting constants in SDC is now more consistently handled CDC and
FP/MCP analysis
- New command line options for BluePearlVVE
- -resetsettings
- Reset all persistent settins for the current user
(irreversible)
- -settingsdir
- Specify directory in which to store .ini file
- Substitutes for default location in Linux and for registry in
Windows
- New command line options for BluePearlCLI
- -verilog_ext, -system_verilog_ext, -vhdl_ext
- Directly set expected file extensions
- Also controllable from GUI, Design Settings →
Language
- New option for MBA and SIG_BITS_LOST check
- CONSTANT_SIZE_STRICT will apply strict evaluation to integer
constants
- Flow status messages are now under message control
- Flow status messages are given the severity setting of
Comment
- Commentseverity is controlable in Preferences and Analysis
Report
- Status now includes current module being elaborated
- User ID and Current Working Directory info has also been added to
the database
- Optional timestamp on each message in log file
- Useful for isolating runtime issues
- Placing flow status under message control enhances the usefulness
of this feature (see New Messages)
- Separate messages for suppressed false and multi-cycle
paths
- Previously, message BPS-0681 noted that a path had been
suppressed for format-incompatible get_netsor
-through
- Now, BPS-0681 is for false paths suppressed for
get_nets, other messages separately specify false paths with
get_nets, multi-cycle paths with get_nets,
and multi-cycle paths with -through
- User ID and Current Working Directory included in
results.db
- Each Load or Analysis run will now include information on who ran
it and from what directory
- This information is reflected in new columns in the Results
Manager and labeling in the Analysis Report
- Enhanced support for Altera libraries
- Support for SuSE 10 and SuSE 11
- New Checks
- POTENTIAL_FSM - Potential Finite State Machine found
- Currently flags case statement under 'if' with reset under
'else'
- PRIORITY_ENCODING - If-then-else chain that could be a case
statement
- New Messages
- BPS-0724 - Potential Finite State Machine found (see new check
above)
- BPS-0725 - Multi-language design requires explicit top
module
- BPS-0726 - Potential Grey Cell Synchronizer
- BPS-0727 - Bad Grey Cell Synchronizer
- BPS-0728 - Priority encoding (see new check above)
- BPS-0729 - Program flow status on a specified circuit element
(see Optional Timestamp above)
- BPS-0730 - Program flow status, no circuit element
specified(see Optional Timestamp above)
- BPS-0731 - CLI option is missing an argument
- BPS-0732 - CLI option is missing an integer long
argument
- BPS-0733 - CLI option is missing an integer argument
- BPS-0734 - CLI option has an invalid argument
- BPS-0735 - Missing input file
- BPS-0736 - Problem reading input file
- BPS-0737 - Could not open -ffile
- BPS-0738 - Bad environmental variable
- BPS-0739 - Recursive reading of -ffile
- BPS-0740 - False path with -throughsuppressed
- BPS-0741 - Multi-cycle path with get_nets
suppressed
- BPS-0742 - Multi-cycle path with -through
suppressed
- BPS-0743 - Skipped Multi-domain path analysis at user
request
List of
Bugs Fixed
- #1550 - User preferences saved on a project basis
- #2065 - Enhanced compilation unit capability
- #2129 - Added option for strict interpretation of integer
constants
- #2132 - Fixed issue with SDC migration
- #2140 - Fixed Windows-only issue
- #2141 - Fixed issue with FTCONNECT check
- #2143 - Support for mixed case component names in programmable
clock files
- #2153 - Report on register initialization
- #2154 - Fixed issue with reporting of combinational
loops
- #2157 - Support for module library search path
- #2160 - Better handling of CDCs when clock is bused
- #2166 - Fixed issue with reading of -f file
- #2169 - Fixed VHDL architecture/entity ambiguity
issue
Blue Pearl Software Suite -- Release 7.2 (Build 7.2.21203)
December 17, 2013
List
of Key Features
- SDC Verification
- Tool now flags issues with port and clock constraints in
user-specified SDC file
- Missing constraints
- Improper multiple constraints
- Improper constraint type (e.g. input port constrained as
output)
- Constraint of non-existent signals
- Six new checks and nine new messages (see below)
- New Methodology-Specific Mode
- Dynamically inserts cross-reference labels into messages, log
file summaries, and documentation
- Current choices:
- Xilinx UltraFast design methodology
- STARC
- Package Summaries Report Option
- Creates log file message summaries on a per-package
basis
- Report Name Prefix
- Adds text prefix to results database label for each analysis
run
- Improved handling of tristates and bidirects
- Improved support of cyclic signals for multi-cycle path
detection
- Tool now recognizes multi-cycle paths due to finite state
machines
- Previously recognized multi-cycle paths with length determined by
e.g. counters
- Now also recognizes similar structures enabled by distinct states
of FSMs
- New Checks
- Checks for SDC Verification
- REPORT_UNCONSTRAINED_PORTS, REPORT_OVERCONSTRAINED_PORTS,
REPORT_MISCONSTRAINED_PORTS, REPORT_UNCONSTRAINED_CLOCKS,
REPORT_OVERCONSTRAINED_CLOCKS, REPORT_MISCONSTRAINED_CLOCKS
- OUT_TRI - Flags top-level tri-state output ports
- CHECK_PATH_ASSERTIONS - Provides control of path validation
messages
- DANG_PIN - Flags unconnected pins of hierarchical
instances
- New Messages
- BPS-0698 thru 700 - Liberty cell error, warning, and informational
messages moved to message system
- BPS-0701 thru 710 - SDC Verification messages, reporting on
improperly constrained signals
- BPS-0711 - Report problem with User Grey Cell information
- BPS-0712 - Flag top-level tristate output ports
- BPS-0713 and 714 - Path validation messages moved to messaging
system
- BPS-0715 and 716 - Messages for new DANG_PIN check for unconnected
instance pin
- BPS-0717 thru 721 - Messages about reading and writing of BPSVDB file
moved to messaging system
List of
Bugs Fixed
- #1511 - Support for listing individual bits in generated SDC
files
- #1535 - Added check crontrol for assertion validation
message
- #1570 - Now supports Cntrl+S for "Save Design" as BPS
file
- #2069 - Program no longer checks HDL code de-activated by
parameters
- #2076-8 - Fixed SystemVerilog issues
- #2086 - Fixed issue instantiating an auto named instance that
already exists
- #2082 - Fixed superfluous "mismatched width" messages related to
SystemVerilog
- #2091 - Implicit port notation not reported for
SystemVerilog interface instantiation
- #2092 - Fixed issue with parameter declarations
(Verific)
- #2093 - Fixed incorrect SystemVerilog bus width
reporting
- #2098 - Fixed issue with incorrect bus width
reporting
- #2099 - Fixed issue with reporting of duplicate case
items
- #2100 - Fixed issue with FSM Viewer
- #2101 - Fixed issue with Liberty file parser for complicated
clocking and data schemes
- #2102 - Fixed issue with message disable feature
- #2103 - Fixed issue with overlapping CDC waivers
- #2104-5 - Fixed issue regarding SystemVerilog struct and previous
assignment overrides
- #2106 - Fixed issue with SystemVerilog interface port
elaboration
- #2109 - Fixed issue regarding SystemVerilog
struct and latches
- #2110 - Fixed issue with SystemVerilog signed wires
- #2111-12 - Fixed issues with Xilinx cells in pure SystemVerilog
designs
- #2115 - Fixed issue with display of state machines
- #2126 - Fixed issue with negative-edge and mixed-edge clocks
during load
- #2132 - Fixed issue with SDC migration and bit-blasted
constraints
Blue Pearl Software Suite -- Release 7.1 (Build 7.1.19827)
September 18, 2013
List
of Key Features
- FPGA Vendor-specific options page
- Xilinx Options page of Design Settings dialog is now within FPGA
Vendor-specific category along with Altera Options
- Xilinx and Altera clocking IP is no longer available by
default
- User must activate these features from vendor-specific options
pages
- Change in licensing
- Distinct flows licensed individually
- No more additive "lowest to highest" in which successive levels
include all preceding levels
- Base tool licenses (gui, cli, analyze) are the only prerequisite
for any other license
- Path analysis now included in base level license
- The labels "Create" and "Analyze Plus" will no longer be
used
- User Grey Cell™ and clock cell capability added
- Can be used to represent 3rd pary IP or legacy circuitry
- Grey Cell capability requires CDC or SDC license
- Can be used to represent user-specified clock synchronization
cells, replacing USER_SPEC_SYNCH
- Option "Disable Translate Off" added to Module Options
- Used to disable "translate_off" declarations
- Allows Blue Pearl to assign user grey-cell information to what
might otherwise be a black box.
- Required for FPGA vendor generated IP
- Major change to CDC flow
- The goal of these changes is to increase flexibility and
granularity
- Check CLK_SYN replaced by fifteen new checks:
- CHECK_FAST_TO_SLOW_CDC
- CHECK_MIXED_CLOCK_EDGE_USAGE
- CHECK_MIXED_TO_DATA_CAPTURES
- CHECK_NEG_TO_MIXED_DATA_CAPTURES
- CHECK_NEG_TO_POS_DATA_CAPTURES
- CHECK_POS_TO_MIXED_DATA_CAPTURES
- CHECK_POS_TO_NEG_DATA_CAPTURES
- CHECK_SYNCH_FANOUT
- REPORT_ON_ALL_CDCS
- REPORT_ON_CONTROL_SYNCH_CLOCK_SIGNAL
- REPORT_ON_DOUBLE_BUF_SYNCH
- REPORT_ON_GRAY_CODE_DOUBLE_BUF_SYNCH
- REPORT_ON_MEM_SYNCH_CELL
- REPORT_ON_UNSYNCH_CDC
- REPORT_ON_USER_SYNCH_CELL
- Check USER_SPEC_SYNCH and its associated package are
gone
- Seven messages associated with USER_SPEC_SYNCH are gone
- Four new messages are introduced to differentiate formerly
consolodated situations
- Deleted message regarding multi-bit unsyncronized paths
(BPS-0178)
- Added message regarding multi-bit double-buffered paths
(BPS-0693)
- CDC Waivers
- Available for CDC Viewer only, no effect on messages
- Permanent part of the design database (stored in
waivers.db)
- Specify delay and clock domain for ports
- Users can assign delay values and clock domains for module
ports
- Added support for auto-detection of black box signal
direction
- New GUI check-box w/ default "on"
- BluePearlVVE now has three command line options
- [filename].bps
- -f [filename].f
- -help
- More consistent behavior of cross-probing and editing
- Right click to open default or external editor from any HDL
View
- Analysis Report HDL View is now consistent with the above
behavior
- Re-arranged menus to be more consistent with Load vs Analyze
functionality
- Port Options and Net Options menus moved to Design Settings from
Analysis Settings
- More items under Start menu in Windows
- Removed many unused messages and some checks
- Message documentation includes Consequences
- Also known as "Why you should care"
- Additional main window toolbar buttons
- Text Reports
- Path Analysis
- FSM Viewer
- Design Summary Report
- Example designs loadable from Help menu
- Apply button added to Preferences menu
- Windows recognizes file type '.bps' as Blue Pearl Software Suite
start file
- Start tool by double-clicking .bps file
- Verbosity controls in GUI have been eliminated
- New Messages
- BPS-0670 - Potential synchronous set/reset
- BSP-0671 thru 679 - Additional clock and reset naming rules
messages
- BPS-0680 - Potential multiple drivers on inout
- BPS-0681 - False or Multi-cycle path not expressed in SDC
file
- BPS-0682 - Potential multiple drivers from black box port treated
as inout
- BPS-0683 - Reset synchronizer synchronously de-asserted
- BPS-0684 - Port instantiation driven by something other than a
signal, such as a function
- BPS-0685 - Direction of black box port has been determined
automatically
- BPS-0686 - Direction of black-box port could not be
determined
- BPS-0687 thru 690 - Regarding mixed-edge data transfers separated
by a latch
- BPS-0691 - Incorrect synchronization of bus by
double-buffering
- BPS-0692 thru 696 - Issues with user grey-cell models
- BPS-0697 - Suppressing internal clock from black box
List of
Bugs Fixed
- #1461 - Support for mixed-case environmental
variables
- #1545 - Changed severity on message re: VHDL variable
declaration
- #1678 - Inout is no longer reported as having multiple
drivers
- #1685 - Clarified text in CDC messages
- #1880 - Misleading error in transcript re: grey cells
- #1962 - Expression used in module instantiation connection is now
a violation
- #1964 - Improved function of NO_SYNCH_DEASSERT_RST
check
- #1992 - Use new message BPS-0670 in place of BPS-0395 when S/R
driven from BB
- #1995 - Fixed SDC file issue w/ false paths and generate
statements
- #1998 - Incorrect constant propagation fixed by allowing values
in more fomats, e.g. 0x, Octal
- #2004 - Fix for improper reading of "little endian" buses from
liberty files
- #2005 - Fix for improper reading of quoted strings from -f
files
- #2006 - Fix for MBA size conflice exclusion option
- #2008 - Fixed naming issue for bused clocks in Cadence SDC
files
- #2017 - Fixed issue with mis-marking of clocks as internal
clocks
- #2042 - Added support for auto-detection of black box signal
direction
- #2062 - Fix for vhdl 2008 libraries
- #2070 - Fix for max occurances of individual
messages
Blue Pearl Software Suite -- Release 7.0 (Build 7.0.17824)
June 12, 2013
List
of Key Features
- Constant propagation is now consistent and
user-controlled
- Various methods for setting constants produce the same
results
- Constant propagation enable check-box added to GUI
- Option -propagate_constant_constraints added to command
line and Tcl set_option
- Enhanced Schematic Viewer capabilities
- User can create custom partial schematics
- Isolate an individual instance
- Trace forward/backward
- Delete unwanted ports and instances
- Features available in all schematic-capable viewers
- Print color schematics
- Max loop limit setting added to Language Options menu
- Applies to "for" and "while" loops in HDL code
- Necessary in program to prevent crashes, infinite loops
- Maximum limit is now user-accessible, no longer
hard-coded
- Enhanced CDC Viewer
- New category "Registered Fanout"
- All Viewers have "Highlight Selection in RTL?" check-box
- On by default
- Turn off to improve response time if RTL files are large or
remotely accessed
- New FSM Viewer, FSM Report, and enhanced FSM analysis
capability
- FSM Analysis checks now run earlier in the tool flow
- List FSMs and all states and transitions
- Graphically displays FSM
- Cross-probes to RTL code
- Note: Linux users must use the CentOS 5.8 build not
supported in the CentOS 4.8 build
- GUI creates and uses "Results/desname.f" file
- Exact GUI run can be more easily re-created on command
line
- Mitigates issue with OS-dependent command length
- FANOUT check now has more options
- In addition to changing the general limit, there are now separate
controls for clocks, set/resets, ports and DFFs
- REGI and REGO can be applied separately to top-module ports and
submodule ports
- Each check has two independent options
- New check - MAX_BUS_WIDTH
- Flags excessively wide buses
- Option to adjust default max
- New check - MAX_LINES_PER_MODULE
- Flags modules or architectures with too many lines of
code
- Option to adjust default max
- New check - ASYNCH_PATHS
- Flags combinational port-to-port paths in all modules
- Enter HDL files recursively
- New dialog box from the Design Settings menu allows the user to
recursively include all HDL files under the selected directory
- Deleted many unused checks and messages
- New messages
- BPS-0656 - State transition detected
- BPS-0657 - Architecture-entity file mismatch
- BPS-0658 - Bus too wide
- BPS-0659 - Port has excessive fanout
- BPS-0660- Set/reset has excessive fanout
- BPS-0661- Clock has excessive fanout
- BPS-0662- Sequential element has excessive
fanout
- BPS-0663- Module/architecture has too many HDL
lines
- BPS-0664 - Incorrect instantiation of Xilinx resource
- BPS-0665 - Asynchronous port-to-port paths
- BPS-0666 - Translation error
- BPS-0667- Topological error
- VERI-9000 - Assign to input in function is warning
List of
Bugs Fixed
- #1400 - Support compilation unit scope with Verific
- #1571 - Functionality of SET_RESET_DISABLED and SET_RESET_ENABLED
is incorrectly linked
- #1580 - CDC Viewer sometimes displays blank
schematics
- #1678 - Fix for MDR message BPS-0009
- #1835 - False CDCs reported for muxed clocks in VHDL
- #1837 - False CDCs reported clock vs. data confusion in
VHDL
- #1838 - False CDCs reported on paths to clock pins in
VHDL
- #1883 - Added user control of loop limit
- #1915 - Separate messages created for driving input in function
(W) vs. non-function (E)
- #1916 - Fix for false BPS-0395 message
- #1920 - The -params file is now tcl format
- #1926 - Add message VERI-9000 to differentiate input assign in
function
- #1927 - Add '*' to vector port names in Cadence SDC
file
- #1930 - Other SDC writing enhancements
- #1933 - Fixed SDC I/O delay command hierarchy and hierarchy
separator
- #1937 - False positive MOS check warning BPS-0563
- #1941 - False BPS-0163 information message
- #1942 - Fix for OS-dependent command line length issue (see ".f"
file feature above)
- #1956 - Fixed false instances of message BPS-0058 for
SystemVerilog
- #1958 - Comment can now start with /// in .f file
- #1960 - Fixed false instnaces of message BPS-0030 for 'include
after port definition
- #1963 - All reports on by default in Xilinx version
- #1967 - Clarified flagging of user-assigned resets
- #1979 - Internal clocks connected to black boxes are now flagged
as such
Blue Pearl Software Suite -- Release 6.3 (Build 6.3.16461)
April 12,2013
List of Key
Features
- Enhancements to CDC Viewer
- CDC Viewer now includes Source and Destination Clock Domain
information and enhanced sorting capability
- New format for Packages→Checks→Messages
- From Design Settings, Analysis Settings, and Analysis Report
Filter, expandable tree-structure replaces cascading sub-windows
Right-hand sub-window always has help file Packages now have help files
help file sub-window is re-sizable
- Enhancements to CDC Viewer
- CDC Viewer now includes Source and Destination Clock Domain
information and enhanced sorting capability
- New format for Packages → Checks → Messages
- From Design Settings, Analysis Settings, and Analysis Report
Filter, expandable tree-structure replaces cascading
sub-windows
- Right-hand sub-window always has help file
- Packages now have help files
- Help file sub-window is re-sizable
- Can now read waivers from command line
- Command line support for message waivers
- Cross-probe to schematic from Analysis Report or Text
Report-table view
- Pull-down for View In Schematic
- Enhanced Schematic Viewer capabilities
- New navigation toolbar
- Fold/unfold selected module (replaces “Flatten”
function)
- Text search capability
- Trace forward/backward from selected net
- Main window transcript opens editor
- Double-clicking on message notices of the form:
[S]-[Prefix]-[####] filename (line#) text
(where the line number is optional) will open the default text editor
to the file and, optionally, line indicated.
- The transcript in the main window is now searchable.
- Detects non-registered outputs and inputs on all modules
- Check REGO previously applied only to top module
- Check REGI added for inputs
- Control individual message limits from the GUI
- Set limits on or disable individual messages using Design
Settings → Messages (in addition to the global limit)
- Check VHDL_CHECKS, CCLP are re-activated
- VHDL_CHECKS looks for objects differentiated only by case, and
for instance names that match their module names.
- CCLP reports loops that are never activated
- Option added to combine Load and Analysis runs
- Option -nobpsvdb ensures that Load and Analysis messages are
viewable simultaneously
- Path Viewer cross-probe capability
- Items in “Path” list cross-probe to schematic
- Text Reports window grays out disabled choices
- The menu in the “Text Reports” window now disables all
unavailable choices so the user knows which reports were not selected
to be generated
- Differentiation between “Load” and “Analysis” checks and
messages
- The GUI and the documentation now make a distinction between
checks (and their associated messages) that run during the “Load”
phase and the “Analysis” phase, or in some cases both
- Several “keyword” checks consolidated
- All “keyword-related” checks are replaced by
FOREIGN_LANGUAGE_KWD. These are:
- SYSTEMVERILOG_KWD
- IEEE_2001_KWD
- IEEE_2005_KWD
- VHDL_KEYWORDS
- Language construct conflict checks are no longer supported
- These are:
- IEEE_2001
- VHDL_2008
- IEEE_2005
- SYSTEMVERILOG
- Persistent window size, location
- Window location and size is now stored for main window size and
sub-window proportions are now stored for Analysis Report
- Analysis Report has local search
- Some pattern matching filter capability is duplicated in main
window
- Analysis Report has enhanced pull-down
- The pull-down menu for each message in the Analysis Report has
additional features:
- Hide All (of this number)
- Set Message Log Limit
- Disable Check
- NESTED_ITE check replaced by ITE_DEPTH
- The NESTED_ITE check is obsolete, replaced by the ITE_DEPTH
check, which performs a superset of the NESTED_ITE operations. Option
setting is also newly supported from the GUI.
- Obsolete messages
- Pertaining to keywords and instance name checks:
- BPS-0157
- BPS-0265
- BPS-0275
- BPS-0444
- BPS-0484
- BPS-0628
List of Bugs Fixed
- #1184 - Check if message ID 293 about clock domain crossing is
redundant
- #1225 - BluePearl incorrectly reports a warning about
non-blocking assignment to a signal
- #1227 - BluePearl incorrectly reports a warning about dangling
nets
- #1243 - Wrong BPS-0372 message: for Clock is as an expression,
when clock/ reset is specified in parenthesis
- #1251 - Comparison of bit widths in assignments (MBA checks) does
not take into account shift operator and constants.
- #1252 - Enhancements to results viewer and 2 fixes
needed
- #1291 - After stopping analysis BluePearl crashes and does not
allow re-running analysis
- #1484 - BP generates message BPS-0250 only when both "NESTED_ITE"
and "ALN" rules are on
- #1607 - BP should write "create_generated_clocks" for gated
clocks
- #1613 - BluePearl writes PSL/SVA assertions for the paths
(internal objects) that don't exist in the design
- #1644 - Allow disabling a check from the Results
viewer.
- #1685 - CDC messages reported incorrectly in the CDC file and
viewer
- #1744 - BluePearl is writing clock as "dummy_clk" for
bi-drectional port IO delay
- #1765 - Spurious BPS-0009 message
- #1812 - BP gives BPS-0395, even though the flops are associated
with a reset
- #1827 - Reporting CDC when there is no CDC in design
- #1836 - Black-box doesn't work for VHDL design
- #1840 - Fixed issue with grey-cell methodology
- #1843 - Testcase crash fixed
- #1846 - Name search capability in Schematic viewer
needed
- #1847 - Path Pane in the Path analysis viewer is
useless
- #1848 - Analysis Report column width issue
- #1850 - Window sizing is not remembered for analysis
settings.
- #1851 - In results viewer ,total Number of Messages status line
does not clearly separate the totals
- #1852 - Window sizing for Design Settings should be
remembered
- #1853 - Analysis report window does not get updated when the
design is re-run
- #1855 - Selecting differnt packages in Analysis Report window
does not update the RTL and message pane
- #1856 - It would be helpful to have a search in the message
list
- #1858 - Re-sizing window within the Analysis Report
window
- #1862 - In Longest Path viewers, under "Path",the instances
should not be editable
- #1866 - Load and Analysis messages should be viewable in the same
summary.
- #1870 - The main transcript window in the GUI should be
searchable
- #1871 - Testcase crashes
- #1876 - Cannot open installation example
bp_install_cehck.bps
- #1878 - When showing the design files under File Name in the
Design Settings Design Files View, it should show the complete path
also.
- #1883 - E-VERI-1066: test.v(29): loop count limit of 5000
exceeded condition is never false
- #1884 - False BPS-0503 message
- #1891 - Opening BP schematic from Analysis Report window
sometimes shows blank schematic
- #1892 - In Analysis reports "Hide all BPS-xxx messages" doesn't
do anything
- #1900 - Xilinx: Report Options appears in 2 places but the option
for ITE is only in one of them.
- #1903 - Schematic for FP is not displayed
- #1911 - reporting incorrect line number for VDB-1000
message
- #1913 - BP gives false BPS 0046 warnings for the
testcase.
Blue Pearl Software Suite -- Release 6.2 (Build
6.2.15343)
February 4,
2013