Lower your design risk with Azure Timing Constraint Validation™
Azure Timing Constraint Validation™ automatically validates timing exception constraints for complex system-on-chip designs, multi-million gate ASIC and FPGA designs. As the number of constraints increases for more complex chip designs, Azure provides a real productivity improvement over any manual, error-prone method of validating constraints. Designs that use many 3rd party IP blocks benefit greatly from using Azure, as designers are not familiar with the IP provided and can spend an enormous amount of time verifying any accompanying constraints.
Azure uses advanced state-space search technology to automatically validate timing exception constraints in Synopsys Design Constraint (SDC) format. This proprietary, innovative technology offers very high performance for large designs at the functional RT level description. The powerful technology allows analysis of false and multicycle path constraints controlled by finite state machines and even sequential control logic. Azure accurately verifies the exact number of cycles for a multicycle path constraint. The actual number of cycles can be hard to specify and is often given a default of 2 cycles for some timing relaxation. Azure, however, will provide the actual number of cycles so that the largest relaxation possible is used for implementation.
Validating timing exception constraints on RTL before synthesis, assures designers that they are using accurate constraints for the implementation process, significantly reducing design risk. Designers often write constraints with wild-cards which cover multiple paths in the design. Such a generalized false path constraint can include a path that is not false, and no timing gets reported at timing analysis (STA). This can result in a timing error that could make the design non-functional. Checking these generalized constraints for accuracy is vital to achieving a correct design. Azure performs a thorough analysis for all specified paths and provides the designer with a much higher level of confidence in the SDC being used to drive synthesis and P&R.
Constraints that are automatically generated by Cobalt Timing Constraint Generation can also be validated with Azure to provide designers with a higher level of confidence and reduced risk. The advantages of using automatically generated constraints from Cobalt are that a much larger, more complete and, accurate set of timing exceptions are generated and used to improve the QoR through design implementation. The iterative, manual, error-prone process of creating sdc timing exceptions can be eliminated by using Cobalt. Much faster timing closure and much faster design implementations can be achieved with a larger and accurate set of timing exceptions. Generating constraints early with Cobalt significantly improves designer productivity.
Azure Timing Constraint Validation is easy to use in any digital design flow. Azure accepts Verilog RTL and SDC timing constraints. Azure rapidly analyzes blocks or full-chip designs to validate the false and multicycle path exceptions in the SDC file. Azure can generate an assertion in Property Specification Language (PSL) or System Verilog Assertion (SVA) formats. If any exception is invalid, Azure will report this error and can also generate a test bench for the counter example. The generated test bench can be used in any simulation environment to verify the result.
Azure Timing Constraint Validation Features:
Reads Verilog RTL (2001)
Reads SDC
Validates false path timing constraints
Validates multicycle path timing constraints
Generates assertions for valid timing exceptions (PSL & SVA)
Generates counter example testbenches for invalid exceptions
Learn more about how Azure can improve designer productivity and lower design risk by reading the datasheet. Please contact Blue Pearl Software’s Sales department if you would like to evaluate Azure Timing Constraint Validation.
