Get faster timing closure with Cobalt Timing Constraint Generation™
Cobalt Timing Constraint Generation™ automatically identifies the timing exceptions in complex, multi-million gate ASIC and FPGA designs. It uses a very advanced symbolic simulation technology that has been optimized to work at the register transfer level (RTL). The high performance technology in Cobalt allows very large, full chip designs to be analyzed. Cobalt analyzes blocks and complete designs and writes out SDC constraints for the timing exceptions which are used to drive RTL synthesis and physical implementation.
Cobalt’s superior technology results in the generation of paths that are safe, irrespective of actual circuit delays.
The timing exception constraints generated by Cobalt are constraints that are very hard to identify manually. Designers only expend the effort to identify such timing exceptions when they experience timing closure issues. Designers waste a lot of time reviewing timing analysis results to determine possible false and multi-cycle paths that need to be specified to attain timing closure. They then have to re-run synthesis or P&R with the new timing exception constraints to see if they can achieve timing closure. These design iterations adversely impact the design schedule.
Cobalt generates the timing exceptions at the RTL design entry level. The false paths and multi-cycle paths are accurately identified and specified in industry standard SDC format. Since Cobalt generates the SDC, the “human” errors in writing the constraints are eliminated. Cobalt identifies a comprehensive set of timing exception constraints improving the probability of success through implementation. The synthesis tools do not have to optimize false paths and have a relaxed timing goal to meet on multi-cycle paths. The timing exception constraints reduce the path optimizations required for synthesis and allow greater degrees of freedom for synthesis tools to optimize the critical paths. A much higher quality of results (QoR) is achieved for the design implementation with Cobalt’s timing exception constraints.
Cobalt Timing Constraint Generation writes assertions for the identified timing exception paths. The assertions can be used in third party tools to verify the timing constraints and to enhance design verification. Cobalt writes SystemVerilog (SVA) and Property Specification Language (PSL) assertions.
Cobalt Feature List:
Fast FSM and control behavior analysis
Sequential analysis of false and multi-cycle paths
Generates timing exception constraints for
Signals crossing clock domains
Resets and constrained signals
Configuration registers
Functional false paths (FPs)
Multicycle paths (MCPs)
Block level MCPs where cyclic signals emanate from block ports
Compares constraints in different files
Migrates block constraints to top-level constraints
Supports .lib descriptions for IP blocks
Generates PSL/SVA assertions for simulation/formal verification
Learn more about Cobalt Timing Constraint Generation. View datasheet. You may also request a copy of the Cobalt White Paper. You are welcome to evaluate Cobalt by registering and downloading the application.
