Indigo identifies functional issues in RTL designs prior to synthesis and resolves timing issues such as synchronization of data crossing clock domains and logic path races.
Indigo analyzes multiple clock domain designs to ensure that data crossing domain boundaries is synchronized, and recognizes double register, memory and custom synchronization schemes and highlights data that re-converges from independent synchronizers. Product features include the ability to quickly identify race conditions, such as write-write, read-write, and combinational loop races, and automatically pin-points the lines of source code that cause them.
Indigo RTL Analysis also includes traditional built-in rule checks that enforce existing design methodologies, including design reuse (RMM/SRS), design for testability (DFT), simulation, synthesis, and lint.
Indigo RTL Analysis datasheet and the product evaluation.
