Blue Pearl Software Product Overview

Introduction to the chip design flow

As process or fabrication technologies advance, chip complexity increases and the design flow becomes more iterative. As illustrated in the diagram below, iterations in the design flow cost money and time that adversely affect the schedule and cost of the devices being designed. In addition, iterations that occur later in the design flow are very expensive, requiring significant time and engineering resources.

graph

Analysis of the causes of iterations that make the design flow unpredictable has shown that resolving timing issues is the major cause, accounting for some 70% of the iterations.

As complexity increases, the manual methods to address timing aspects by ASIC (Application Specific Integrated Circuit) and FPGA (Field Programmable Gate Arrays) engineers are proving to be insufficient for the high performance and very complex chips that are becoming the norm.

Engineers are discovering functional timing issues one at a time as they work through the implementation process and then writing timing constraints for each one followed by another synthesis and place and route run to find the next issue. This wastes days or weeks as the tools work inefficiently and engineers have to spend a large amount of time debugging the causes and writing timing constraints manually.

Timing constraints in the chip design flow

ASIC and FPGA designers who write behavioral RTL are implementing a design from a design specification. They write in Hardware Design Languages (HDLs) such as Verilog and VHDL which are generically described as RTL or Register Transfer Languages.

These high-level behavioral descriptions are synthesized to a gate level netlist for a specific technology. To meet the functional and speed requirements of the chip, designers have to also write design constraints to guide the tools in the synthesis flow. Constraints are used to control the output of the optimization and mapping process from synthesis. Constraints provide goals that the optimization and mapping processes have to meet and control the structural implementation of the design. Constraints are written to control area, timing, power and testability.

Timing constraints are the most challenging for designers to create in complex designs because the process is manual and error-prone. Frequently the constraints are incomplete, resulting in inefficient tool performance and accounting for the majority of design iterations in the chip design flow.

The tool performance for synthesis and layout, also known as place and route, can be slowed down by more than 10X only to provide a result that does not meet the speed requirements for the design due to incorrect or incomplete timing constraints. The designers have to debug the issues, write new timing constraints and then run the tools again to try and achieve a design implementation that works. This design iteration wastes time, increases the costs of design and makes the chip development unpredictable. When iterations occur after synthesis, say from place and route, the time and costs are significantly increased. If the silicon is made with a bug or is non-functional, companies incur very high respin costs, project delays and perhaps missed market windows that devour all the profitability from the chip development.

Blue Pearl Software's Solution

Blue Pearl Software has developed proprietary technologies to automatically generate and validate timing constraints for false and multi-cycle paths. False and multi-cycle paths are the most difficult timing exceptions to identify and verify and, if they are not all constrained, the implementation tools optimize such paths unnecessarily.

False paths are paths that cannot be sensitized or are logically impossible paths that do not have to meet the clock speed or timing requirements. Multi-cycle paths are paths that take 2 or more clock cycles due to the controlling logic on a path between registers. The timing constraint on such paths can be relaxed by the number of clock cycles the path takes which relieves the optimization process in synthesis considerably.

Blue Pearl Software's tools analyze the design to understand the intended behavior at the RTL level and extract the clocks if they are not specified. They then perform path analysis to identify false and multi-cycle paths as the tool understands the control logic and the functional intent. The tool automatically generates timing constraints for these exception paths and writes out the constraints in SDC (Synopsys Design Constraint) format, which is an industry standard for ASIC and FPGA designs. The automation helps designers by generating a complete set of false and multi-cycle path constraints, early, at the functional level, so that the implementation of the chip can be driven more productively with fewer iterations.

graph2

Blue Pearl is optimizing the chip design flow by providing automated, easy to use tools that work at RTL or the functional level to generate false and multi-cycle path constraints to drive the synthesis design flow more productively. The tools also validate existing timing constraints for false and multi-cycle paths. This is very important for design reuse methodologies and ASIC manufacturers, ensuring that incorrect constraints are not specified which could cause catastrophic results for the chip design. A complete timing path analysis tool flow is depicted below and more information is available by contacting Blue Pearl Software.

graph 3