Blue Pearl Software has three breakthrough products that operate on synthesizable RTL, offering high performance and the capacity to run on full-chip ASIC and FPGA designs.
Indigo RTL Analysis™
Functional design analysis that checks functional properties, methodology standards and design rules to speed-up writing of correct RTL code that is compatible with tools in digital design flows, for better quality of results (QoR).
Cobalt Timing Constraint Generation™
Identifies false and multi-cycle paths from RTL descriptions and writes SDC timing constraints for implementation as well as SVA or PSL assertions for verification. Cobalt reduces iterations in the flow to achieve timing closure faster.
Azure Timing Constraint Validation™
Validates existing timing exception constraints in SDC format for block or full-chip RTL designs to lower risks of design implementation.
Blue Pearl Software’s tools are seamlessly integrated in a single executable and are designed to be easy to use. All inputs and outputs are industry standards so that it is easy to integrate in digital design flows. The advanced technology used in Blue Pearl’s tools allows very fast performance and accurate results. To learn more about the benefits of the technology please go to “Introduction to the Chip Design Flow”.
Indigo
AnalysisRTL
(now available)
Predict Chip Functionality at the RTL Level. Analyze functional RTL descriptions. Full chip designs are analyzed blazingly fast. Indigo RTL Analysis is more accurate than structural analysis and is the market price leader.
Cobalt (now available)
Automatic Timing Constraint Generation
Identify false and multi-cycle paths instead of correcting problems during chip implementation. Generate SDC while writing RTL. Write out SVA for verification. Close timing faster with higher QoR.
Azure (now
available)
Automatic Timing Constraint Validation
Automatically validate SDC for false and multi-cycle paths. Output testbench for counter-example. Avoid error-prone manual validation. Significantly reduce your overall design risk.
