Today’s modern Electronic Design Automation (EDA) tools are built to solve the most challenging of design problems. For IP, FPGA and ASIC design, most tools are developed leveraging modern software development methodologies such as Agile software design. Many also implement their software using languages that foster code reuse such as OOAD. EDA vendors, including Blue Pearl, use these techniques to improve the tools development cycle and quality assurance. One of the missions of Blue Pearl, has always been to try to enable modern software techniques for RTL hardware designers.
Blue Pearl’s Visual Verification Suite provides easy-to-use structural & formal analysis for advanced linting, CDC analysis & debug. What is new, is now we are also providing a documented verification methodology to speed user development and improve overall RTL quality.
Read this article to learn more about Blue Pearl Verification Methodology.
About the Blue Pearl Verification Methodology
The Blue Pearl Software Verification Methodology is a set of best practices and recommendations intended to streamline verification and signoff of IP, FPGA and ASIC RTL. The methodology is intended to be used in conjunction with the Visual Verification Suite to reduce design risk and to accelerate development.
The Visual Verification Suite performs static and formal analysis of RTL based on a series of rules and guidelines that reflect good coding practice, finding common errors that can cause issues such as hardware vs. simulation mismatches and metastability caused by Clock Domain Crossings and Reset circuity. When these rules are breached, the tool flags the potential bugs within that code for review or waiver by the design engineer. The goal of this methodology is to reduce “noise” or “false positive” results by providing a step-by-step sequence that allows the engineer to most efficiently decide which of the potential bugs can be waived and which need to be fixed.
The document is intended to be used by Design Engineers who are developing new RTL for new designs and building on legacy designs, and by Verification Engineers who must verify the entire design.
The guide includes high-level information, guidelines and recommendations for the following topics:
- Chapter 2: Setting up your design for validation: This chapter covers options such as top down vs. bottom up verification, leveraging legacy design, 3rd party IP and imported projects from Intel, Microsemi and Xilinx.
- Chapter 3: Methodology overview: This chapter includes high level suggestions to reduce noisy analysis so that you can focus on the most important warnings and errors.
- Chapter 4: Static Analysis: This chapter will walk you through best practices for statically analyzing designs to eliminate structural issues prior to simulation and synthesis.
- Chapter 5: Management Dashboard: This chapter will discuss how to set up RTL signoff and track progress over time.
- Chapter 6: Advanced Static Analysis and Clock Domain Crossing Analysis: This chapter will discuss setting up your design for CDC analysis and best practices to avoid metastability.
- Chapter 7: Leveraging the Visual Verification Suite in your environment: This chapter covers running in revision control environments and moving between Tcl command line mode and the Graphical User Interface.
Download the entire Blue Pearl Verification Methodology Guide