FPGAs routinely have millions of gates with memories, transceivers, third party IP and processor cores. Problems can be time consuming and complex to debug in the lab and through simulations. Designers need verification tools that can identify problems quickly to reduce their verification and debug time before simulation, before synthesis, and definitely before burning chips in the lab.
Why Analyze RTL™?
- IEEE Verilog/System Verilog & VHDL language specification compliance and syntax
- User configurable checks along with standard checks, STARC, and Xilinx UltraFast
- GUI to streamline debug; integrated RTL, Schematic, and message viewer
- Easy debug message sorting, filtering and waiving to pinpoint problems
- Flow automation, Command Line Interface (CLI), and re-usable message waiver file
- Decrease learning time with Setup Wizard
Identifies Design Issues Quickly
The Visual Verification Environment enables Analyze RTL™ users to debug design issues quickly using intelligent sorting and message filtering. The key features include low Noise, check customization for specific design style, easy setup, and waiver migration.
RTL Checks for High Speed Designs
It is important to find as early as possible RTL coding that prevents the design from getting desired speed. In FPGAs, because their fabric is more constrained than an ASIC, certain types of structures causes slow downs. Rather than wait for synthesis or static timing analysis results, Analyze RTL™ users can easily identify high fanout nets, deeply nested “if-then-else” statements, excessively long logic paths, and poor reset methodology.
Blue Pearl’s Analyze RTL™ combines the ease-of-use methodology and extensive analysis of super-lint tools with the power of formal verification into a single high performance, high capacity design checking solution. With Blue Pearl, you get a unique combination of powerful built-in checks and formal analysis that gives you the most comprehensive and powerful static design checking capability available. Deploy Blue Pearl early and eliminate complex design errors at all stages of your design implementation cycle and drastically reduce the amount of effort you spend finding bugs later using time-consuming traditional test-bench methods.
The Blue Pearl Visual Verification environment consists of tools that allow you to evaluate, verify, understand and take full advantage of the constraints and assertions generated by the Blue Pearl Software Suite.
The tools consist of three dockable sub-windows within a main schematic window. In the Schematic Viewer, you see the entire circuit. The first sub-window in the Schematic Viewer is a hierarchical design browser that lets you quickly navigate through a large hierarchical system.
The other two sub-windows are the “HDL View” showing an HDL source file and the “Mini View” schematic window.
Finite State Machine (FSM) Analysis
The Analyze RTL system includes FSM analysis capabilities. FSMs will automatically be extracted from the RTL design, the FSM states analyzed for dead and/or terminal states and a visual representation of each FSM generated which includes the states and transitions.
Pre-synthesis Longest Path Analysis
Blue Pearl Software offers an innovative solution to finding the critical paths early in the design cycle. Instead of waiting for synthesis, place and route & static timing analysis to complete before finding the critical paths, Blue Pearl’s path analysis can find the longest paths (correlated to the critical paths) at the RTL phase. Designers now have a powerful and easy-to-use tool that will pinpoint the problem areas that prevent achieving required performance.
Mode-based Path Analysis
As more functionality is packed into electronics devices, designers are using an enormous number of clocks and multiple switches to place their circuits in different design modes, which then activate and/or deactivate certain portions of the design. Blue Pearl Software provides a simple approach to find the mode-dependent critical paths. The Blue Pearl Software Suite performs mode-based path analysis by allowing the user to set certain signals to specific values.
The usability of lint, the power of formal verification
Blue Pearl Software offers an innovative validation tool that simplifies and speeds up design checking. We uniquely combine the easy-to-use, almost push-button, methodology of traditional rule checking / lint tools with the power of formal verification technology, putting powerful property checking capability at your fingertips.
Automatically extract design properties
Blue Pearl Software quickly performs an exhaustive search of the design’s state space using symbolic simulation and powerful design analysis techniques to verify hundreds of automatically extracted design properties including:
Detect races before simulation
Blue Pearl identifies race conditions, such as write-write, read-write, and combinational loop races, and automatically pin-points the lines of source code that are the cause of the race conditions.
Enforce your design methodology & customize rules
Find design for testability errors at RTL stage
Blue Pearl allows you to check that your RTL complies with design for testability (DFT) rules, reducing the amount of time and effort spent at the gate level finding and fixing scan DFT violations. You can perform scan-path integrity and ATPG checks, and you can check that your JTAG 1149.1 boundary scan test controller or custom test controller operates correctly, all at the register transfer level before you synthesize to gates.
Be productive immediately
Blue Pearl speeds up debugging by providing accurate feedback for property violations, taking you right to the source of the error in your RTL code.
Analyze RTL™ Checks
Analyze rapidly performs many hundreds of checks including the following:
- Drive conflicts
- X-source problems
- Design initializes / resets
- Redundant logic
- Assignment checks
- Simulation / Synthesis
- Implied latches
- Case statements
- Size conflicts
- Coding Style
In addition to offering the ability to customize your own packages of checks, Analyze includes the following standard packages:
- Reuse Methodology Manual
- Principles of Verifiable RTL
- Design for Testability
- Semiconductor Reuse Standard
- Cycle Based Simulation