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Create Timing Constraints™

Why Create Timing Constraints™?

Designs are increasingly becoming larger and more complex. They often have embedded processors, intellectual property, other pre-existing modules and multiple clocks. As these designs push the limits of area, power, and performance, the fastest timing routes quickly become congested and it gets more difficult to optimize for performance.

Timing constraints, which include clock rates, I/O delays, and timing exceptions, direct the synthesis and place & route tools to achieve the necessary timing targets to meet performance requirements and close timing quickly.

It is very difficult to manually identify timing exceptions. With billions of paths in a single design, these timing exceptions are often incomplete or inaccurate, making timing closure the single most time-consuming task, next to verification.

Visual Verification

The Blue Pearl Visual Verification environment consists of four tools that allow you to evaluate, verify, understand and take full advantage of the constraints and assertions generated by the Blue Pearl Software Suite. The False & Multi-cycle Path Audit Trail Viewer and the Assertion Audit Trail Viewer are associated with the Create product.
Both tools consist of three dockable sub-windows within a main schematic window that show a color-coded view of only the selected path. The first sub-window in the Assertion Audit Trail Viewer is a list of assertions. Selecting an assertion from this list opens a filterable list of false paths associated with that assertion. The first sub-window in the False & Multi-cycle Path Audit Trail Viewer (see below) is a filterable list of false and multi-cycle paths from the current design.

 

The Solution

The solution is to automatically generate a set of compact, efficient, effective constraints using a conservative approach, irrespective of circuit, so that the constraints are valid. The right tool should work at both the RTL and gate level. Why? Because verification is faster and more accurate at RTL.

Common causes of timing closure delays:

  • Designing with an incomplete set of constraints
  • Accidentally introducing errors in timing exceptions
  • Multiple design iterations
  • Over-constrained or under-constrained designs
  • Timing failure
  • Difficulty identifying very complex multi-cycle paths

Superior technology

The Blue Pearl Software Suite is built with industry-leading symbolic simulation technology to automatically generate the timing exceptions from RTL code. With Blue Pearl, designers can accomplish in just a few short hours what might normally take designers many weeks of work.

Features & Benefits:

  • Fast FSM and control behavior analysis
  • Sequential analysis of false and multi-cycle paths
  • Generates timing exception constraints for:
    • - Capitalize signals in signals crossing
      clock domains
    • - Resets and constrained signals
    • - Configuration registers
    • - Functional false paths (FPs)
    • - Multicycle paths (MCPs)
    • - Block level MCPs where cyclic signalsemanate from block ports
  • Compares constraints in different SDC files
  • Migrates block constraints to top-level constraints

 
  • Supports .lib descriptions for IP blocks
  • Generates PSL/SVA assertions for simulation/ formal verification

Multiple levels of reassurance

If a single tool could actually produce complex false and multi-cycle paths that are nearly impossible for designers to produce, how valuable would that be to you?

  • Automatically identify timing exceptions in complex, multi-million gate ASIC and FPGA designs.
  • Use highly advanced symbolic simulation optimized to run at the register transfer level (RTL) where verification is faster.
  • Analyze blocks and complete designs and write out SDC constraints for timing exceptions which are used to drive RTL synthesis and physical implementation.

Blue Pearl’s superior technology generates paths that are safe, irrespective of actual circuit delays.

  • Avoid silicon re-spins
  • Predict design schedules
  • Increase IP re-use
  • Reduce time-to-market
  • Improved design quality

 

Compare methodologies

Create Automatic Timing Constraint Generation Manual Timing Exception Generation No Timing Exceptions
Complete set of constraints prior to synthesis Partial set of constraints prior to synthesis n/a
Fewer design iterations Multiple design iterations Multiple design iterations
Fast run-times Painstaking and time consuming Difficult to meet timing requirements
Error free Error prone n/a
Maximum optimization for area & power Partial optimization for area & power Sacrifice area & power
Best in class chip performance chip performance Sacrifice chip performance
Easy to close timing Difficult to close timing Extremely difficult to close timing

Language Support

  • Verilog
  • VHDL
  • SystemVerilog
  • Mixed Languages
  • Liberty (.Lib)
  • SDC

 

Outputs

  • SDC
  • PSL (Property Specification Language) Assertions
  • SVA (System Verilog Assertions)

 

Platforms Supported

  • Linux
  • Windows

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