The Blue Pearl Software Suite is fast and easy to use, accelerates a defined fixed rate for designs errors, and runs on Linux and Windows.
Automates the manual timing constraints generation process
Blue Pearl automates the manual process of timing constraints generation at the functional design stage. The constraints drive the efficiency of downstream synthesis and place & route tools.
Accelerates ASIC and FPGA Verification
Blue Pearl finds the bugs early in the flow and the intelligent filtering enables designers to focus on real problems.