Blue Pearl Software Inc

Accelerates IP & FPGA Verification

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How can Blue Pearl Software Help?

DVCON 2016

Fix Your Design Issues with Blue Pearl Software

Analyze RTLTM

Analyze RTL

Analyze RTL™ finds mistakes in design descriptions.

Clock Domain Crossing (CDC)

Clock Domain Crossing (CDC)

Identifies missing clock domain crossings (CDC) synchronizer issues.

Automatic SDC Generation

Automatic SDC Generation

Finds false and multi-cycle paths from RTL descriptions.

What Customers are Saying?

"We use SDC to generate timing exceptions and have found that SDC runs very fast and produces accurate constraints at RTL."

- Jauher Zaidi, CEO Palmchip Corporation

"Using SDC helped us quickly generate timing exception constraints that improved the timing on our design by 30% after synthesis and placement in a Magma flow."

- Joe Dao, CAD Manager, Aeluros

"At Fujitsu, we use Analyze RTL™ from Blue Pearl Software to find bugs in the netlist early when they are easier to fix. From our experience, we can find bugs that could potentially save a tapeout."

- Mike James, Director, VLSI Technology, Fujitsu

FPGA market focus

The Blue Pearl Software Suite is fast and easy to use, is priced for the FPGA community and runs on registered linux and windows.

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Automates the manual timing constraints generation process

Blue Pearl automates the manual process of timing constraints generation at the functional design stage. The constraints drive the efficiency of downstream synthesis and place & route tools.

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Accelerates IP and FPGA Verification

Blue Pearl finds the bugs early in the flow and the intelligent filtering enables designers to focus on real problems.

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Blue Pearl Software Suite

The Blue Pearl Software Suite includes RTL design analysis – linting, clock domain crossing analysis and automatic timing constraint (SDC) generation, that accelerates IP and FPGA verification.