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Fix Your Design Issues with Blue Pearl Software

Analyze RTLTM

Analyze RTL

Analyze RTL™ finds mistakes in design descriptions.

Clock Domain Crossing (CDC)

Clock Domain Crossing (CDC)

Identifies missing clock domain crossings (CDC) synchronizer issues.

Automatic SDC Generation

Automatic SDC Generation

Finds false and multi-cycle paths from RTL descriptions.

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Market Focus

The Blue Pearl Software Suite is fast and easy to use, accelerates a defined fixed rate for designs errors, and runs on Linux and Windows.

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Automate1

Automates the manual timing constraints generation process

Blue Pearl automates the manual process of timing constraints generation at the functional design stage. The constraints drive the efficiency of downstream synthesis and place & route tools.

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Accelerate_rocket

Accelerates ASIC and FPGA Verification

Blue Pearl finds the bugs early in the flow and the intelligent filtering enables designers to focus on real problems.

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Blue Pearl Software Suite

The Blue Pearl Software Suite includes RTL design analysis – linting, clock domain cross Analysis and automatic timing constrain (SDC) generation, that accelerates ASIC, IP and FPGA verification.