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As FPGA complexity increases, designers cannot start verification in the lab or rely solely on simulation and synthesis. In fact, verification should start during the RTL development stage.
If you are targeting Xilinx devices use the UltraFsat design methodology. Using Analyze RTL accelerates adoption of the UltraFast methodology and ensures optimized implementation for targeted devices.Learn more
The Blue Pearl Software Suite works with the Xilinx Vivado™ Design Suite running on Windows and Linux platforms.
Our solution for RTL analysis includes linting, clock domain crossing (CDC) and automatic Synopsys Design Constraint (SDC) generation. With our SDCs, we make the synthesis and place and route phases of FPGA design implementation more efficient. Our Visual Verification Environment™ makes it easy to use for any level of FPGA designers to validate their constraints.
Blue Pearl provides high performance, innovative, automated tools to generate and validate critical timing and functional information early in the design cycle. Watch Ellis share the genesis of Blue Pearl.”Learn More
“Analyze RTL™ is the base product and has two options, CDC and SDC. Provides functional design analysis to verify properties, methodology standards and design rules. Reduces time spent writing...”
“Identifies clock domain crossings (CDC) issues for designs with multiple clock domains. Includes the Grey Cell™ and User Grey Cell™ methodologies that enable inter-IP analysis ...”
"Blue Pearl Software is an electronic design automation (EDA) company that offers a unique and powerful approach to improving the process of designing computer chips or integrated circuits (ICs) which power electronic systems such as iPOD's, cell-phones, PDA's, and PC's..."
“Identifies false and multi-cycle paths from RTL descriptions and writes SDC timing constraints for...”