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Come learn how the optimized integration of Xilinx Vivado with the Blue Pearl Software Suite allows FPGA designers to find their RTL bugs quickly while reducing their design risk”Learn More and Register
The Blue Pearl Software Suite works with the Xilinx Vivado™ Design Suite running on Windows and Linux platforms.
Our solution for RTL analysis includes linting, clock domain crossing (CDC) and automatic Synopsys Design Constraint (SDC) generation. With our SDCs, we make the synthesis and place and route phases of FPGA design implementation more efficient. Our Visual Verification Environment™ makes it easy to use for any level of FPGA designers to validate their constraints.
Blue Pearl provides high performance, innovative, automated tools to generate and validate critical timing and functional information early in the design cycle. Watch Ellis share the genesis of Blue Pearl.”Learn More
“Provides functional design analysis to verify properties, methodology standards and design rules. Reduces time spent writing...”
“Identifies false and multi-cycle paths from RTL descriptions and writes SDC timing constraints for...”
"Blue Pearl Software is an electronic design automation (EDA) company that offers a unique and powerful approach to improving the process of designing computer chips or integrated circuits (ICs) which power electronic systems such as iPOD's, cell-phones, PDA's, and PC's..."
“Download our datasheet, whitepapers, and application notes to learn more about the Blue Pearl Software Suite.”