Blue Pearl Software Inc. - FPGA Designers, ASIC Designers, clock domain, Clock Domain Crossing (CDC), False Path, Multi-Cycle Path, SDC constraints, SDC, linting, DRC, timing constraints, design rules, design compliance, RTL analysis, timing closure, assertion, SVA, PSL.

Accelerating FPGA Implementation with Xilinx Vivado™

The Blue Pearl Software Suite works with the Xilinx Vivado™ Design Suite running on Windows and Linux platforms.
Our solution for RTL analysis includes linting, clock domain crossing (CDC) and automatic Synopsys Design Constraint (SDC) generation. With our SDCs, we make the synthesis and place and route phases of FPGA design implementation more efficient. Our Visual Verification Environment™ makes it easy to use for any level of FPGA designers to validate their constraints.

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Jauher Zaidi, CEO Palmchip Corporation
“We use Create to generate timing exceptions for our challenging design blocks for Palmchip SoC Platform and IP blocks and have found that Create runs very fast and produces accurate constraints at RTL.”
Mike James, Director, VLSI Technology, Fujitsu
“At Fujitsu, we use Analyze RTL Analysis from Blue Pearl Software to find bugs in the netlist early when they are easier to fix. From our experience, we can find bugs that could potentially save a tapeout.”
Brian Daellenbach, President of Northwest Logic
“Using Analyze, we have identified and resolved coding issues that help us maximize the quality of our IP Cores”
Steve Presant, VP of Engineering, C2 Microsystems
“Blue Pearl has allowed us to create a low risk, predictable development cycle that helps generate accurate RTL code, reducing time-consuming iterations.”
Samir Shroff, VP Engineering, Sibridge Technologies.
“Blue Pearl Software’s latest tool allows us to rapidly view design analysis results, including clock domain crossings and timing constraints, ensuring that our customers receive the highest quality verification IP available at this time.”
Carl Ruggiero, CEO, Trilinear Technologies.
“Blue Pearl Software’s latest capability allows us to selectively weigh logic elements and rapidly determine the longest paths rather than wait for long and expensive synthesis runs, thus enabling us to provide reliable products while reducing our design cycle.”

Discover Blue Pearl

Blue Pearl Software is a privately held EDA (Electronic Design Automation) company that develops software to improve productivity of semiconductor chip design. Blue Pearl provides high performance, innovative, automated tools to generate and validate critical timing and functional information early in the design cycle. Designers using Blue Pearl's solutions can lower design risk, improve the quality of results, save time and reduce the cost of their chip design process.

Blue Pearl Software at DAC 2013

Accelerating FPGA Implementation with Xilinx Vivado™

Blue Pearl Software Suite Takes the Pain out of FPGA Synthesis

The genesis of Blue Pearl Software by Ellis Smith, CEO

Welcome to Blue Pearl Software Inc.

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Jauher Zaidi, CEO Palmchip Corporation

Mike James, Director, VLSI Technology, Fujitsu

Brian Daellenbach, President of Northwest Logic

Steve Presant, VP of Engineering, C2 Microsystems

Samir Shroff, VP Engineering, Sibridge Technologies.

Carl Ruggiero, CEO, Trilinear Technologies.

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