Clock Domain Crossing (CDC)


The Blue Pearl Software Suite offers the capability to analyze ASIC and FPGA designs for Clock Domain Crossing (CDC) issues:

  1. – Finds places in design that don’t have CDC synchronization that cause metastability
  2. – Identifies CDC synchronization types
  3. – Has IP block modeling capability that reduces complexity and accommodates lack of model availability
  4. – Has reports and schematic to understand and debug CDC synchronization
  5. – Easy setup by identifying clocks and FPGA clock generators.
  6. – CDC is an option to Analyze RTL™, the base product within the software suite.

Download Visual Verification Suite and request your 45 day Starter Edition License and get started today


  • Analyze CDCs from a GUI or in batch mode
  • Easily run CDC analysis using different scenarios
  • Easy setup with specific group checks
  • Full TCL parser to read in familiar inputs where clocks and domains have already been defined
  • Identify synchronization issues between interacting clocks
  • Clock Domain Crossing Analysis Types:
    1. – Missing synchronizers
    2. – Re-converging nets
    3. – Combinational logic in synchronizers
    4. – Combinational logic before synchronizers

Ease of Setup

Blue Pearl eases design set up with automatic Clock and reset identification, SDC input of Domain information, understanding of clock generator blocks to propagate clocks and our advanced clock interaction diagram.


User Grey Cell (UGC) for IP-based Designs

In a typical flow, designers have to black box their generated or non-synthesizable IPs. The resulting CDC analysis is incomplete and does not report many CDC issues that lead to metastability in the field. With Blue Pearl’s User Grey Cell™ (UGC) methodology, CDC issues across boundary interfaces can be identified. Blue Pearl contains vendor UGC models and UGCs are easy to create from your databook.


Understand Vendor Clock Schemes

Most CDC tools do not understand vendor clock schemes. Designers thus spend enormous resources to set up their design. Blue Pearl’s CDC has built-in intelligence such that with minimal effort, designers can set up their CDC run and debug using the built-in cross-probing and schematic display.

As chip complexity rises, designers are increasingly relying on advanced multi-clocking techniques and IP integration to address their time-to-market, high-performance and low-power requirements. CDC offers clock domain crossing analysis, pre-synthesis longest path and Grey Cell methodologies to solve these issues.


Detect clock domain synchronization errors

Blue Pearl supports multiple clock designs. Formal clock domain boundary checking ensures that data that crosses clock domain boundaries is synchronized. Blue Pearl recognizes common synchronization schemes such as double register buffering, first-in first-out (FIFO) register file based synchronization, and multiplexed control based synchronization as well as customized synchronization schemes. For custom schemes, you can specify allowed synchronization cells. Blue Pearl also identifies data that is generated and consumed by different edges of the same clock and checks for the appropriate use of lock-up latches.

User Grey Cell™
In many complex designs, engineers only have access to protected or non-synthesizable IPs. They resort to black box methodologies, which are inconclusive for inter-IP RTL analysis. Using the User Grey Cell methodology, designers can perform inter-IP analysis across the whole design. Click here for more information.

Visual Verification
The Blue Pearl Visual Verification environment consists of tools that allow you to evaluate, verify, understand and take full advantage of the constraints and assertions generated by the Blue Pearl Software Suite.

The tools consist of three dockable sub-windows within a main schematic window. In the Clock Domain Crossing Viewer you see a color-coded view of only the selected path. The first sub-window in the Clock Domain Crossing Viewer (see below) is a filterable list of CDCs from the current design.

The other two sub-windows are the “HDL View” showing an HDL source file and the “Mini View” schematic window.

Language Support

  • Verilog
  • VHDL
  • SystemVerilog
  • Mixed languages
  • Liberty (.Lib)

Platforms Supported

  • Linux
  • Windows