Guarantee high reliability RTL with the Visual Verification Suite Management Dashboard.The Blue Pearl Management Dashboard delivers real-time visibility to ASIC, FPGA and IP RTL design rule and CDC checks to better assess schedules, risk and overall design quality.
This standalone option to the Visual Verification Suite, provides RTL Designers, Verification Engineers and Managers visual insight into the RTL verification progress, run to run, providing graphical reports on the number of fixed and outstanding Messages, Clock Domain Crossing issues and Waivers. The Design Sign off dashboard can be customized to ensure the code has been analyzed and has passed all user defined mandatory checks.
These graphical reports, generated for both GUI and Tcl flows, can be customized and exported for use in documentation and design reviews.
- Monitors and logs messages, Clock Domain Crossings and Waivers day to day and per run to provide real-time visibility into the RTL verification progress
- Customize report to omit or show errors, warnings, comments and information.
- Works for both interactive and batch runs, making it useful for individual system designs.
- Easily exported in Microsoft Office tools for inclusion into documentation and standard reports, making it ideal for program updates and design reviews.
- Runs on both Windows and Linux operating systems
Time and Risk Management
You can’t manage what you can’t measure. Providing visual insight into the progress of the design cycle allows designers and managers to track and monitor the verification progress. The Management Dashboard tracks progress both day to day, and run to run, enabling more accurate schedule forecasting and overall cost to design cycle closure. With real-time visibility to the project status, users can see what’s been fixed, waived and still needs to be worked.
Reports can be generated for both GUI and Tcl flows and are easily exported to Microsoft Office Tools, making documentation for design reviews quick and easy.
- Unsynchronized Clock Domain Crossings can cause serious issues and are difficult to debug.
- The CDC Dashboard brings real-time updates on the number of CDCs in the design and reports whether they have been synchronized or not.
- Run to run comparisons makes tracking easy and fast.
Key features of the Visual Verification Suite are the Advanced Clock Environment and Clock Domain Crossing Analysis. Together they pinpoint potential metastability issues in a design caused by unsynchronized clocks. The CDC Dashboard view enables RTL Designers,Verification Engineers and Managers to see progress on these issues providing real-time visibility into the type of synchronizers that have been applied, or if the issue was waived by the user.
Understanding What Has Been Waived
- Accidental or intentional waiving of critical issues can result in nonfunctioning silicon
- The Management Waivers Dashboard brings visibility to all waivers to ensure they are truly nonissues
Key to understanding where the design is in the verification progress, is knowing what has been waived, either as Must Fix or Will Not Fix. While a user might have good reason to initially waive an issue, reaching verification signoff requires all Must Fix issues to be addressed.The Waivers dashboard is critical going into design reviews to ensure critical issues do not make it through verification without the visibility and accountability they require.
Achieving Signoff Verification
- Signoff report with easy setup for ‘company specific’ RTL signoff rules.
- Customizable for one’s company specific Design Rule Checks.
- User defined Design Signoff criteria.
The Design Signoff Dashboard provides details on which checks have been run, and whether they passed or not. With easy to customize signoffcriteria, users pick which checks must be run and pass before signoff is complete. With multiple Signoff Criteria sets allowed, designers can be confident in knowing the design conforms to their corporate policies for “clean” RTL.