Blog

What Makes a Great Verification Methodology

Today’s modern Electronic Design Automation (EDA) tools are built to solve the most challenging of design problems. For IP, FPGA and ASIC design, most tools are developed leveraging modern software development methodologies such as Agile software design. Many also implement their software using languages that foster code reuse such as OOAD. EDA vendors, including Blue […]

Read More
 

The Value of High Reliability RTL for FPGA Design

John Molyneux, COO & Senior VP Sales and Marketing, Blue Pearl Software Introduction Today’s FPGA designs are typically developed by assembling between 50 to 100 unique IP blocks to form a complete System on Chip (SoC) including embedded processors, high speed serial interfaces, analog, signal processing and control logic. These systems are large, complex and […]

Read More
 

Tcl scripts and managing messages in ASIC & FPGA debug

Our previous Blue Pearl post looked at the breadth of contextual visualization capability in the GUI to speed up debug. Two other important aspects of the ASIC & FPGA pre-synthesis workflow are automating analysis with scripts and managing the stream of messages produced. Let’s look at these aspects in the latest Blue Pearl 2016.1 release. […]

Read More
 

Cross-viewing improves ASIC & FPGA debug efficiency

We introduced the philosophy behind the Blue Pearl Software suite of tools for front-end analysis of ASIC & FPGA designs in a recent post. As we said in that discussion, effective automation helps find and remedy issues as each re-synthesis potentially turns up new defects. Why do Blue Pearl users say their tool suite is […]

Read More
 

FPGA tools for more predictive needs in critical

“Find bugs earlier.” Every software developer has heard that mantra. In many ways, SoC and FPGA design has become very similar to software development – but in a few crucial ways, it is very different. Those differences raise a new question we should be asking about uncovering defects: earlier than when? Structured development methodology was […]

Read More
 

Where Does RTL lint tool fit in my design flow?

Working with ASIC and particularly FPGA designers, I’m frequently asked if finding bugs using existing simulation or emulation tools is sufficient. The short answer is “Yes”,but it’s not always the most efficient. As design sizes increase but schedules do not expand to match, designers find themselves frustrated by spending too much time looking at simulation […]

Read More
 

Nice to be back, especially at DAC 52

Did you stop by booth # 832 and check out Blue Pearl Software’s awesome new and improved RTL debugging environment version 9.1? If not, hopefully you took a spin down Central Park on our big screen, won an Apple watch, or at least picked up our tchotchke for your little ones at home. As for […]

Read More