Products

Blue Pearl Products

The Blue Pearl Visual Verification Suite provides a comprehensive set of verification tools for development high reliability RTL. Created for ASIC, FPGA and IP RTL developers, the suite’s offers Analyze RTL™ linting and debug, Clock Domain Crossing analysis and Synopsys Design Constraints (SDC) generation. These solutions are proven to run over 60X faster than alternative tools while they improve quality-of-results (QoR), reduce risk and decrease development time. The Visual Verification Environment complements RTL simulation by ensuring code and SDC quality along with clocking integrity. Engineered to maximize RTL find/fix rates, the Visual Verification Suite uniquely provides easy setup, consistent results, Management Dashboard for complete push-button analytics, and runs on both Linux and Windows.

Advanced Clock Environment

Blue Pearl Software’s ACE offers the capability to visualize clocks and asynchronous clock domain crossings in RTL designs to help users analyze their design for CDC metastability.

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Analyze RTL™
Provides functional design analysis to verify properties, methodology standards and design rules. Reduces time spent writing accurate RTL code that is compatible with tools in digital design flows. Lowers design risk and improves quality of results (QoR).

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CDC
As chip complexity rises, designers are increasingly relying on advanced multi-clocking techniques and IP integration to address their time-to-market, high-performance and low-power requirements. Analyze Plus offers full-chip clock domain crossing (CDC), pre-synthesis longest path and Grey Cell methodologies to solve these critical issues.

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Management Dashboard
The Blue Pearl Management Dashboard delivers real-time visibility to ASIC, FPGA and IP RTL design rule and CDC checks to better assess schedules, risk and overall design quality.

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SDC
Identifies false and multi-cycle paths from RTL descriptions and writes SDC timing constraints for implementation as well as SVA or PSL assertions for verification. Create reduces iterations in the flow to achieve timing closure faster, minimizing design risk.

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