Blue Pearl Products

Blue Pearl Software has pioneered new technologies which operate directly on synthesizable RTL, offering high performance and the capacity to run on full-chip ASIC and FPGA designs.

Analyze RTL™

Provides functional design analysis to verify properties, methodology standards and design rules. Reduces time spent writing accurate RTL code that is compatible with tools in digital design flows. Lowers design risk and improves quality of results (QoR).


CDC Option

As chip complexity rises, designers are increasingly relying on advanced multi-clocking techniques and IP integration to address their time-to-market, high-performance and low-power requirements. Analyze Plus offers full-chip clock domain crossing (CDC), pre-synthesis longest path and Grey Cell methodologies to solve these critical issues.


SDC Option

Identifies false and multi-cycle paths from RTL descriptions and writes SDC timing constraints for implementation as well as SVA or PSL assertions for verification. Create reduces iterations in the flow to achieve timing closure faster, minimizing design risk.