Announcing Visual Verification Suite 2017.3

SANTA CLARA, California – Nov 8, 2017 – Blue Pearl Software, Inc., the leading provider of design automation software for ASIC, FPGA and IP RTL verification, today announced immediate availability of the Visual Verification Suite 2017.3.

The Visual Verification Suite provides an advanced integrated RTL debugging, constraint generation and clock domain crossing analysis and debug environment, so that designers can verify as they code. With the suite, RTL developers produce the highest level of quality code, in the least amount of time. It is proven to help avoid costly and time-consuming design re-spins due to simulation vs. hardware mismatches, structural issues, invalid constraints and metastability issues. The new release provides updates to the suites Analyze RTL’s advanced static and formal analysis, Clock Domain Crossing (CDC) analysis and the Management Dashboard tools.

The release features up to 12X faster runtimes for CDC Analysis, enabling faster iterations of analysis and debug. “With the enhanced CDC infrastructure, built in FPGA libraries and recently patented User Grey Cell technology which enables CDC analysis through encrypted IP,  we are setting the bar in ease of use and performance,” said Scott Aron Bloom, CTO at Blue Pearl.

The release also features enhancements to the Xilinx® Vivado® Design Suite integration  introduced in 2017.2. Users can now use the Blue Pearl Tcl App, to track key metrics run-to-run from Vivado, such as Max Frequency, Power, Device Utilization and display it in the Management Dashboard’s graphs and new table views along with results from the Visual Versification Suite. The Management Dashboard streamlines design reviews, audits, signoff and revision control.

Engineered to maximize RTL bug find/fix rates for both novice and expert users, the Visual Verification Suite 2017.3 uniquely provides easy setup, support for ASICs and FPGAs, consistent results, a DO-254 verification package, and runs on both Linux and Windows.

Availability:

Download today and follow the new Blue Pearl Verification Methodology to accelerate your RTL verification. For additional information please review the release notes or contact your local sales representative.

About Blue Pearl Software

Blue Pearl Software, Inc. is a leading provider of design automation software for ASIC, FPGA and IP RTL verification. Our customers are RTL managers and developers, in military, aerospace, semiconductor, medical, communications and safety critical design companies, who wish to avoid costly and time-consuming design spins due to simulation / HW mismatches, invalid constraints and clocking issues. The Visual Verification Suite is designed, tested and supported in the United States of America.

Press Contact:

Jenn Treiber, Blue Pearl Software, +1- 408.961.0121, x341
 jenn.treiber@bluepearlsoftware.com