Join David E. Wallace PhD, Chief Scientist
for "Using Static RTL Analysis to Accelerate Satellite FPGA Verification"
Verification Processes and Methodologies Session
DVCON 2020Wednesday March 04, 3:00 pmLearn More
Smart editor verifies as you code
Analyze RTL™ finds mistakes in design descriptions.
Identifies missing clock domain crossings (CDC) synchronizer issues.
Finds false and multi-cycle paths from RTL descriptions.
Real-time visibility to ASIC, FPGA and IP RTL design rule and CDC checks
The Visual Verification Suite includes RTL design analysis – linting, clock domain crossing analysis and automatic timing constraint (SDC) generation that accelerates ASIC, FPGA and IP verification.