Visit Blue Pearl Software at XDF to learn how to Verify as you Code!
October 1-2, 2019 - Fairmont, San Jose, CA
November 12-13, 2019 - World Forum, The Hague, Netherlands
December 3-4, 2019 - China National Convention Center, Beijing, China
Smart editor verifies as you code
Analyze RTL™ finds mistakes in design descriptions.
Identifies missing clock domain crossings (CDC) synchronizer issues.
Finds false and multi-cycle paths from RTL descriptions.
Real-time visibility to ASIC, FPGA and IP RTL design rule and CDC checks
The Visual Verification Suite includes RTL design analysis – linting, clock domain crossing analysis and automatic timing constraint (SDC) generation that accelerates ASIC, FPGA and IP verification.