Blue Pearl’s Adam Taylor to present “Identifying & correcting difficult to find RTL problems earlier” at the FPGAworld Conference 2019
SANTA CLARA, California –Sept. 11, 2019 – Blue Pearl Software, Inc., a leading provider of design automation software for ASIC, FPGA and IP RTL verification, announced today that Professor Adam Taylor will be presenting a session at the FPGAworld conference events in Stockholm Sweden on September 17 and Copenhagen Denmark on September 19. The session, titled “Identifying & correcting difficult to find RTL problems earlier”, explores common design issues that are found late in the development process. The talk will focus on how to quickly find and fix structural and clock domain crossing issues using Blue Pearl’s Visual Verification™ Suite.
In addition, Blue Pearl will showcase the latest version of their Visual Verification Suite. With the Visual Verification Suite, designers verify as they code. The suite features HDL Creator™ smart editor, Analyze™ RTL advanced static and formal linting, an integrated debug environment, enhanced Clock Domain Crossing (CDC) analysis and automated SDC generation. An integrated Management Dashboard is also provided to track progress and deliver signoff statistics for audits and design reviews.
Stop by the Blue Pearl booth and have our experts show you how to verify as you code and discuss how to obtain your free* 6-month HDL Creator license to get started.
Not Attending FPGAworld?
- Read Adam’s latest blogs
- Try out the Visual Verification Suite Starter Edition
- Read the Blue Pearl Verification Methodology Guide
- Read more about the Visual Verification Suite
About Blue Pearl Software
Blue Pearl Software, Inc. is a leading provider of DO-254 compatible design automation software for ASIC, FPGA and IP RTL verification. Our customers are RTL managers and developers in military, aerospace, semiconductor, medical, communications and safety critical design companies. The Visual Verification™ Suite speeds block and project level verification with advanced integrated RTL structural and formal linting, constraint generation and clock domain crossing analysis. Our usability is unmatched in the industry and can help your design team accelerate development and produce high reliability designs. The Visual Verification Suite is designed, tested and supported in the United States of America.
* Free 6-month HDL Creator license is limited to qualified active FPGA or ASIC students, designers or managers and will be provided within two weeks following the event.
Jenn Treiber, Blue Pearl Software, +1- 408.961.0121, x341