Blog

Issue 10: No, Latches are (mostly) not OK in FPGA Design

FPGA designs are increasingly used for high reliability applications such as aerospace, medical, industrial, and automotive. Failure of the FPGA design in these applications could lead to injury, loss of life or environmental disaster. It is therefore critical that the design behaves as we intend and not as the synthesis or implementation tool thinks it […]

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Issue 9: High Reliability FSM and Counter Support

In our journey of exploring the Blue Pearl Visual Verification Suite’s capabilities we will examine how it can help us create better finite state machines (FSMs) and counters. FSMs are of course the central element of programmable logic designs. This is especially true when we are creating mission critical orhigh reliability solutions where the use […]

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Issue 8: RTL Coding for Space and High Reliability Applications

Thanks to their performance, flexibility and “any-to”outstanding interfacing capabilities, FPGAs are incredibly popular in high reliability applications. They are often used in space systems such as satellites, launchers, aerospace, and autonomous vehicles. In these high reliability applications, depending upon the use case, the system must be able to keep operating or gracefully and safely fail, […]

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Issue 7: Five Capabilities You Might Not Know About Visual Verification Suite

The capabilities for Blue Pearl’s Visual Verification Suite are well known for Lint, Clock Domain Crossing Analysis and Design Management. However, there are several capabilities in the tool which are easily overlooked but nevertheless provide the designer with significant benefits, let’slook at five of these. 1. Text Reports – Along with the linting and messages […]

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Blue Pearl Software’s continued commitment to customers

Individuals and businesses alike are taking steps to reduce the risk associated with the spread of coronavirus (COVID-19). Our foremost concern is that everyone takes the appropriate precautions for the safety of themselves, their families, and co-workers. Blue Pearl Software wants to enable the productivity of our current and potential customers in this challenging environment. […]

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Issue 6: BPS Integration with Vivado and Vivado HLS

Modern FPGA designs are complex systems. They may include processor cores, RTL code and, increasingly, modules developed using High Level Synthesis (HLS). Of course, we still want to analyse the custom RTL created and the overall design for compliance with design methodologies e.g. STARC, Reuse Methodology Manual and Xilinx UltraFast Design Methodologies. We may also […]

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Issue 5: State Machine Design & Analysis

State machines are at the heart of our designs. They enable us to implement sequential structures in a parallel programmable logic world. We use them to implement control structures and communication protocols, however complex state machines design can also significantly slow down our development due to the challenges associated in debugging issues, epically if only […]

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Issue 4: Creating our own Packages

One of the reasons we use Blue Pearl’s Visual Verification™ Suite is to enter simulation and synthesis with a better quality of code. Improved code quality means we have identified and addressed coding standard violations, structural logic issues, long combinatorial paths and of course, clock domain crossing issues. To ensure the same quality across several […]

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Issue 3: Working with Xilinx Parameterized Macros for CDC

When it comes to crossing clock domains it is best, if possible, to implement the crossing using registers which are located close together and have small set up and hold windows. In short, our register structures used for clock domain crossing should be optimized for signals which may go metastable. In our Xilinx designs this […]

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Issue 2: Identifying & correcting difficult to find RTL problems earlier

All engineers know the earlier we identify an issue in our design, the easier and less costly it is to correct. We also know some issues are easier than others to identify. The worst kind are those which are intermittent and manifest late in the test regime or, even worse, in the field. These late […]

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